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Issue 196 - Breakpad processor support for x86-64. r=mento
git-svn-id: http://google-breakpad.googlecode.com/svn/trunk@227 4c0a9323-5329-0410-9bdc-e9ce6186880e
This commit is contained in:
ted.mielczarek
@@ -215,6 +215,160 @@ typedef struct {
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#define MD_CONTEXT_CPU_MASK 0xffffffc0
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/*
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* AMD64 support, see WINNT.H
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*/
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typedef struct {
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u_int16_t control_word;
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u_int16_t status_word;
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u_int8_t tag_word;
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u_int8_t reserved1;
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u_int16_t error_opcode;
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u_int32_t error_offset;
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u_int16_t error_selector;
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u_int16_t reserved2;
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u_int32_t data_offset;
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u_int16_t data_selector;
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u_int16_t reserved3;
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u_int32_t mx_csr;
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u_int32_t mx_csr_mask;
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u_int128_t float_registers[8];
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u_int128_t xmm_registers[16];
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u_int8_t reserved4[96];
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} MDXmmSaveArea32AMD64; /* XMM_SAVE_AREA32 */
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#define MD_CONTEXT_AMD64_VR_COUNT 26
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typedef struct {
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/*
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* Register parameter home addresses.
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*/
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u_int64_t p1_home;
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u_int64_t p2_home;
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u_int64_t p3_home;
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u_int64_t p4_home;
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u_int64_t p5_home;
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u_int64_t p6_home;
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/* The next field determines the layout of the structure, and which parts
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* of it are populated */
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u_int32_t context_flags;
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u_int32_t mx_csr;
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/* The next register is included with MD_CONTEXT_AMD64_CONTROL */
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u_int16_t cs;
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/* The next 4 registers are included with MD_CONTEXT_AMD64_SEGMENTS */
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u_int16_t ds;
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u_int16_t es;
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u_int16_t fs;
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u_int16_t gs;
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/* The next 2 registers are included with MD_CONTEXT_AMD64_CONTROL */
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u_int16_t ss;
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u_int32_t eflags;
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/* The next 6 registers are included with MD_CONTEXT_AMD64_DEBUG_REGISTERS */
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u_int64_t dr0;
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u_int64_t dr1;
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u_int64_t dr2;
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u_int64_t dr3;
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u_int64_t dr6;
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u_int64_t dr7;
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/* The next 4 registers are included with MD_CONTEXT_AMD64_INTEGER */
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u_int64_t rax;
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u_int64_t rcx;
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u_int64_t rdx;
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u_int64_t rbx;
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/* The next register is included with MD_CONTEXT_AMD64_CONTROL */
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u_int64_t rsp;
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/* The next 11 registers are included with MD_CONTEXT_AMD64_INTEGER */
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u_int64_t rbp;
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u_int64_t rsi;
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u_int64_t rdi;
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u_int64_t r8;
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u_int64_t r9;
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u_int64_t r10;
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u_int64_t r11;
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u_int64_t r12;
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u_int64_t r13;
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u_int64_t r14;
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u_int64_t r15;
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/* The next register is included with MD_CONTEXT_AMD64_CONTROL */
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u_int64_t rip;
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/* The next set of registers are included with
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* MD_CONTEXT_AMD64_FLOATING_POINT
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*/
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union {
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MDXmmSaveArea32AMD64 flt_save;
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struct {
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u_int128_t header[2];
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u_int128_t legacy[8];
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u_int128_t xmm0;
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u_int128_t xmm1;
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u_int128_t xmm2;
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u_int128_t xmm3;
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u_int128_t xmm4;
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u_int128_t xmm5;
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u_int128_t xmm6;
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u_int128_t xmm7;
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u_int128_t xmm8;
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u_int128_t xmm9;
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u_int128_t xmm10;
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u_int128_t xmm11;
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u_int128_t xmm12;
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u_int128_t xmm13;
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u_int128_t xmm14;
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u_int128_t xmm15;
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} sse_registers;
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};
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u_int128_t vector_register[MD_CONTEXT_AMD64_VR_COUNT];
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u_int64_t vector_control;
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/* The next 5 registers are included with MD_CONTEXT_AMD64_DEBUG_REGISTERS */
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u_int64_t debug_control;
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u_int64_t last_branch_to_rip;
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u_int64_t last_branch_from_rip;
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u_int64_t last_exception_to_rip;
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u_int64_t last_exception_from_rip;
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} MDRawContextAMD64; /* CONTEXT */
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/* For (MDRawContextAMD64).context_flags. These values indicate the type of
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* context stored in the structure. The high 26 bits identify the CPU, the
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* low 6 bits identify the type of context saved. */
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#define MD_CONTEXT_AMD64_CONTROL (MD_CONTEXT_AMD64 | 0x00000001)
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/* CONTEXT_CONTROL */
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#define MD_CONTEXT_AMD64_INTEGER (MD_CONTEXT_AMD64 | 0x00000002)
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/* CONTEXT_INTEGER */
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#define MD_CONTEXT_AMD64_SEGMENTS (MD_CONTEXT_AMD64 | 0x00000004)
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/* CONTEXT_SEGMENTS */
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#define MD_CONTEXT_AMD64_FLOATING_POINT (MD_CONTEXT_AMD64 | 0x00000008)
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/* CONTEXT_FLOATING_POINT */
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#define MD_CONTEXT_AMD64_DEBUG_REGISTERS (MD_CONTEXT_AMD64 | 0x00000010)
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/* CONTEXT_DEBUG_REGISTERS */
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/* WinNT.h refers to CONTEXT_MMX_REGISTERS but doesn't appear to define it
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* I think it really means CONTEXT_FLOATING_POINT.
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*/
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#define MD_CONTEXT_AMD64_FULL (MD_CONTEXT_AMD64_CONTROL | \
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MD_CONTEXT_AMD64_INTEGER | \
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MD_CONTEXT_AMD64_FLOATING_POINT)
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/* CONTEXT_FULL */
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#define MD_CONTEXT_AMD64_ALL (MD_CONTEXT_AMD64_FULL | \
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MD_CONTEXT_AMD64_SEGMENTS | \
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MD_CONTEXT_X86_DEBUG_REGISTERS)
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/* CONTEXT_ALL */
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/*
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* SPARC support, see (solaris)sys/procfs_isa.h also
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*/
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