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A64: Implement FMIN's vector single and double precision variants

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This commit is contained in:
Lioncash
2018-07-07 15:29:53 -04:00
committed by MerryMage
parent 7b03da86c2
commit 009879d92b
2 changed files with 16 additions and 1 deletions
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src/frontend/A64/decoder/a64.inc
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@@ -738,7 +738,7 @@ INST(BIC_asimd_reg, "BIC (vector, register)", "0Q001
INST(FMLS_vec_2, "FMLS (vector)", "0Q0011101z1mmmmm110011nnnnnddddd")
INST(FSUB_2, "FSUB (vector)", "0Q0011101z1mmmmm110101nnnnnddddd")
//INST(FMLSL_vec_1, "FMLSL, FMLSL2 (vector)", "0Q0011101z1mmmmm111011nnnnnddddd")
//INST(FMIN_2, "FMIN (vector)", "0Q0011101z1mmmmm111101nnnnnddddd")
INST(FMIN_2, "FMIN (vector)", "0Q0011101z1mmmmm111101nnnnnddddd")
INST(FRSQRTS_4, "FRSQRTS", "0Q0011101z1mmmmm111111nnnnnddddd")
INST(ORR_asimd_reg, "ORR (vector, register)", "0Q001110101mmmmm000111nnnnnddddd")
INST(ORN_asimd, "ORN (vector)", "0Q001110111mmmmm000111nnnnnddddd")