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Merge pull request #569 from lioncash/t32-misc

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thumb32: Implement miscellaneous category instructions
This commit is contained in:
merry
2021-02-01 21:06:36 +00:00
committed by GitHub
parent e01583abba 36fc596a51
commit 0e26e8a531
5 changed files with 346 additions and 39 deletions
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1
src/CMakeLists.txt
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@@ -151,6 +151,7 @@ if ("A32" IN_LIST DYNARMIC_FRONTENDS)
frontend/A32/translate/impl/synchronization.cpp
frontend/A32/translate/impl/thumb16.cpp
frontend/A32/translate/impl/thumb32.cpp
frontend/A32/translate/impl/thumb32_misc.cpp
frontend/A32/translate/impl/translate_arm.h
frontend/A32/translate/impl/translate_thumb.h
frontend/A32/translate/impl/vfp.cpp

20
src/frontend/A32/decoder/thumb32.h
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@@ -275,16 +275,16 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
//INST(&V::thumb32_UHSUB8, "UHSUB8", "111110101100----1111----0110----"),
// Miscellaneous Operations
//INST(&V::thumb32_QADD, "QADD", "111110101000----1111----1000----"),
//INST(&V::thumb32_QDADD, "QDADD", "111110101000----1111----1001----"),
//INST(&V::thumb32_QSUB, "QSUB", "111110101000----1111----1010----"),
//INST(&V::thumb32_QDSUB, "QDSUB", "111110101000----1111----1011----"),
//INST(&V::thumb32_REV, "REV", "111110101001----1111----1000----"),
//INST(&V::thumb32_REV16, "REV16", "111110101001----1111----1001----"),
//INST(&V::thumb32_RBIT, "RBIT", "111110101001----1111----1010----"),
//INST(&V::thumb32_REVSH, "REVSH", "111110101001----1111----1011----"),
//INST(&V::thumb32_SEL, "SEL", "111110101010----1111----1000----"),
//INST(&V::thumb32_CLZ, "CLZ", "111110101011----1111----1000----"),
INST(&V::thumb32_QADD, "QADD", "111110101000nnnn1111dddd1000mmmm"),
INST(&V::thumb32_QDADD, "QDADD", "111110101000nnnn1111dddd1001mmmm"),
INST(&V::thumb32_QSUB, "QSUB", "111110101000nnnn1111dddd1010mmmm"),
INST(&V::thumb32_QDSUB, "QDSUB", "111110101000nnnn1111dddd1011mmmm"),
INST(&V::thumb32_REV, "REV", "111110101001nnnn1111dddd1000mmmm"),
INST(&V::thumb32_REV16, "REV16", "111110101001nnnn1111dddd1001mmmm"),
INST(&V::thumb32_RBIT, "RBIT", "111110101001nnnn1111dddd1010mmmm"),
INST(&V::thumb32_REVSH, "REVSH", "111110101001nnnn1111dddd1011mmmm"),
INST(&V::thumb32_SEL, "SEL", "111110101010nnnn1111dddd1000mmmm"),
INST(&V::thumb32_CLZ, "CLZ", "111110101011nnnn1111dddd1000mmmm"),
// Multiply, Multiply Accumulate, and Absolute Difference
//INST(&V::thumb32_MUL, "MUL", "111110110000----1111----0000----"),

157
src/frontend/A32/translate/impl/thumb32_misc.cpp Normal file
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@@ -0,0 +1,157 @@
/* This file is part of the dynarmic project.
* Copyright (c) 2016 MerryMage
* SPDX-License-Identifier: 0BSD
*/
#include "frontend/A32/translate/impl/translate_thumb.h"
namespace Dynarmic::A32 {
bool ThumbTranslatorVisitor::thumb32_CLZ(Reg n, Reg d, Reg m) {
if (m != n || d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const auto reg_m = ir.GetRegister(m);
const auto result = ir.CountLeadingZeros(reg_m);
ir.SetRegister(d, result);
return true;
}
bool ThumbTranslatorVisitor::thumb32_QADD(Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const auto reg_m = ir.GetRegister(m);
const auto reg_n = ir.GetRegister(n);
const auto result = ir.SignedSaturatedAdd(reg_m, reg_n);
ir.SetRegister(d, result.result);
ir.OrQFlag(result.overflow);
return true;
}
bool ThumbTranslatorVisitor::thumb32_QDADD(Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const auto reg_m = ir.GetRegister(m);
const auto reg_n = ir.GetRegister(n);
const auto doubled_n = ir.SignedSaturatedAdd(reg_n, reg_n);
ir.OrQFlag(doubled_n.overflow);
const auto result = ir.SignedSaturatedAdd(reg_m, doubled_n.result);
ir.SetRegister(d, result.result);
ir.OrQFlag(result.overflow);
return true;
}
bool ThumbTranslatorVisitor::thumb32_QDSUB(Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const auto reg_m = ir.GetRegister(m);
const auto reg_n = ir.GetRegister(n);
const auto doubled_n = ir.SignedSaturatedAdd(reg_n, reg_n);
ir.OrQFlag(doubled_n.overflow);
const auto result = ir.SignedSaturatedSub(reg_m, doubled_n.result);
ir.SetRegister(d, result.result);
ir.OrQFlag(result.overflow);
return true;
}
bool ThumbTranslatorVisitor::thumb32_QSUB(Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const auto reg_m = ir.GetRegister(m);
const auto reg_n = ir.GetRegister(n);
const auto result = ir.SignedSaturatedSub(reg_m, reg_n);
ir.SetRegister(d, result.result);
ir.OrQFlag(result.overflow);
return true;
}
bool ThumbTranslatorVisitor::thumb32_RBIT(Reg n, Reg d, Reg m) {
if (m != n || d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const IR::U32 swapped = ir.ByteReverseWord(ir.GetRegister(m));
// ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4)
const IR::U32 first_lsr = ir.LogicalShiftRight(ir.And(swapped, ir.Imm32(0xF0F0F0F0)), ir.Imm8(4));
const IR::U32 first_lsl = ir.LogicalShiftLeft(ir.And(swapped, ir.Imm32(0x0F0F0F0F)), ir.Imm8(4));
const IR::U32 corrected = ir.Or(first_lsl, first_lsr);
// ((x & 0x88888888) >> 3) | ((x & 0x44444444) >> 1) |
// ((x & 0x22222222) << 1) | ((x & 0x11111111) << 3)
const IR::U32 second_lsr = ir.LogicalShiftRight(ir.And(corrected, ir.Imm32(0x88888888)), ir.Imm8(3));
const IR::U32 third_lsr = ir.LogicalShiftRight(ir.And(corrected, ir.Imm32(0x44444444)), ir.Imm8(1));
const IR::U32 second_lsl = ir.LogicalShiftLeft(ir.And(corrected, ir.Imm32(0x22222222)), ir.Imm8(1));
const IR::U32 third_lsl = ir.LogicalShiftLeft(ir.And(corrected, ir.Imm32(0x11111111)), ir.Imm8(3));
const IR::U32 result = ir.Or(ir.Or(ir.Or(second_lsr, third_lsr), second_lsl), third_lsl);
ir.SetRegister(d, result);
return true;
}
bool ThumbTranslatorVisitor::thumb32_REV(Reg n, Reg d, Reg m) {
if (m != n || d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const auto result = ir.ByteReverseWord(ir.GetRegister(m));
ir.SetRegister(d, result);
return true;
}
bool ThumbTranslatorVisitor::thumb32_REV16(Reg n, Reg d, Reg m) {
if (m != n || d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const auto reg_m = ir.GetRegister(m);
const auto lo = ir.And(ir.LogicalShiftRight(reg_m, ir.Imm8(8), ir.Imm1(0)).result, ir.Imm32(0x00FF00FF));
const auto hi = ir.And(ir.LogicalShiftLeft(reg_m, ir.Imm8(8), ir.Imm1(0)).result, ir.Imm32(0xFF00FF00));
const auto result = ir.Or(lo, hi);
ir.SetRegister(d, result);
return true;
}
bool ThumbTranslatorVisitor::thumb32_REVSH(Reg n, Reg d, Reg m) {
if (m != n || d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const auto reg_m = ir.GetRegister(m);
const auto rev_half = ir.ByteReverseHalf(ir.LeastSignificantHalf(reg_m));
ir.SetRegister(d, ir.SignExtendHalfToWord(rev_half));
return true;
}
bool ThumbTranslatorVisitor::thumb32_SEL(Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const auto reg_m = ir.GetRegister(m);
const auto reg_n = ir.GetRegister(n);
const auto result = ir.PackedSelect(ir.GetGEFlags(), reg_m, reg_n);
ir.SetRegister(d, result);
return true;
}
} // namespace Dynarmic::A32

12
src/frontend/A32/translate/impl/translate_thumb.h
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@@ -115,6 +115,18 @@ struct ThumbTranslatorVisitor final {
bool thumb32_BL_imm(Imm<11> hi, Imm<11> lo);
bool thumb32_BLX_imm(Imm<11> hi, Imm<11> lo);
bool thumb32_UDF();
// thumb32 miscellaneous instructions
bool thumb32_CLZ(Reg n, Reg d, Reg m);
bool thumb32_QADD(Reg n, Reg d, Reg m);
bool thumb32_QDADD(Reg n, Reg d, Reg m);
bool thumb32_QDSUB(Reg n, Reg d, Reg m);
bool thumb32_QSUB(Reg n, Reg d, Reg m);
bool thumb32_RBIT(Reg n, Reg d, Reg m);
bool thumb32_REV(Reg n, Reg d, Reg m);
bool thumb32_REV16(Reg n, Reg d, Reg m);
bool thumb32_REVSH(Reg n, Reg d, Reg m);
bool thumb32_SEL(Reg n, Reg d, Reg m);
};
} // namespace Dynarmic::A32