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IR: Generalise SignedSaturated{Add,Sub} to support more bitwidths

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This commit is contained in:
MerryMage
2018-07-30 10:59:52 +01:00
parent 71db0e67ae
commit 10e196480f
4 changed files with 119 additions and 43 deletions
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40
src/frontend/ir/ir_emitter.cpp
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@@ -481,15 +481,43 @@ U32U64 IREmitter::MinUnsigned(const U32U64& a, const U32U64& b) {
return Inst<U64>(Opcode::MinUnsigned64, a, b);
}
ResultAndOverflow<U32> IREmitter::SignedSaturatedAdd(const U32& a, const U32& b) {
auto result = Inst<U32>(Opcode::SignedSaturatedAdd, a, b);
auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
ResultAndOverflow<UAny> IREmitter::SignedSaturatedAdd(const UAny& a, const UAny& b) {
ASSERT(a.GetType() == b.GetType());
const auto result = [&]() -> IR::UAny {
switch (a.GetType()) {
case IR::Type::U8:
return Inst<U8>(Opcode::SignedSaturatedAdd8, a, b);
case IR::Type::U16:
return Inst<U16>(Opcode::SignedSaturatedAdd16, a, b);
case IR::Type::U32:
return Inst<U32>(Opcode::SignedSaturatedAdd32, a, b);
case IR::Type::U64:
return Inst<U64>(Opcode::SignedSaturatedAdd64, a, b);
default:
return IR::UAny{};
}
}();
const auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
return {result, overflow};
}
ResultAndOverflow<U32> IREmitter::SignedSaturatedSub(const U32& a, const U32& b) {
auto result = Inst<U32>(Opcode::SignedSaturatedSub, a, b);
auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
ResultAndOverflow<UAny> IREmitter::SignedSaturatedSub(const UAny& a, const UAny& b) {
ASSERT(a.GetType() == b.GetType());
const auto result = [&]() -> IR::UAny {
switch (a.GetType()) {
case IR::Type::U8:
return Inst<U8>(Opcode::SignedSaturatedSub8, a, b);
case IR::Type::U16:
return Inst<U16>(Opcode::SignedSaturatedSub16, a, b);
case IR::Type::U32:
return Inst<U32>(Opcode::SignedSaturatedSub32, a, b);
case IR::Type::U64:
return Inst<U64>(Opcode::SignedSaturatedSub64, a, b);
default:
return IR::UAny{};
}
}();
const auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
return {result, overflow};
}

4
src/frontend/ir/ir_emitter.h
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@@ -142,8 +142,8 @@ public:
U32U64 MinSigned(const U32U64& a, const U32U64& b);
U32U64 MinUnsigned(const U32U64& a, const U32U64& b);
ResultAndOverflow<U32> SignedSaturatedAdd(const U32& a, const U32& b);
ResultAndOverflow<U32> SignedSaturatedSub(const U32& a, const U32& b);
ResultAndOverflow<UAny> SignedSaturatedAdd(const UAny& a, const UAny& b);
ResultAndOverflow<UAny> SignedSaturatedSub(const UAny& a, const UAny& b);
ResultAndOverflow<U32> UnsignedSaturation(const U32& a, size_t bit_size_to_saturate_to);
ResultAndOverflow<U32> SignedSaturation(const U32& a, size_t bit_size_to_saturate_to);

20
src/frontend/ir/opcodes.inc
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@@ -76,10 +76,10 @@ A64OPC(GetTPIDRRO, T::U64,
// Hints
OPCODE(PushRSB, T::Void, T::U64 )
// Pseudo-operation, handled special ly at final emit
OPCODE(GetCarryFromOp, T::U1, T::U32 )
OPCODE(GetOverflowFromOp, T::U1, T::U32 )
OPCODE(GetGEFromOp, T::U32, T::U32 )
// Pseudo-operation, handled specially at final emit
OPCODE(GetCarryFromOp, T::U1, T::Opaque )
OPCODE(GetOverflowFromOp, T::U1, T::Opaque )
OPCODE(GetGEFromOp, T::U32, T::Opaque )
OPCODE(GetNZCVFromOp, T::NZCVFlags, T::Opaque )
OPCODE(NZCVFromPackedFlags, T::NZCVFlags, T::U32 )
@@ -155,10 +155,16 @@ OPCODE(MinUnsigned32, T::U32, T::U32,
OPCODE(MinUnsigned64, T::U64, T::U64, T::U64 )
// Saturated instructions
OPCODE(SignedSaturatedAdd, T::U32, T::U32, T::U32 )
OPCODE(SignedSaturatedSub, T::U32, T::U32, T::U32 )
OPCODE(UnsignedSaturation, T::U32, T::U32, T::U8 )
OPCODE(SignedSaturatedAdd8, T::U8, T::U8, T::U8 )
OPCODE(SignedSaturatedAdd16, T::U16, T::U16, T::U16 )
OPCODE(SignedSaturatedAdd32, T::U32, T::U32, T::U32 )
OPCODE(SignedSaturatedAdd64, T::U64, T::U64, T::U64 )
OPCODE(SignedSaturatedSub8, T::U8, T::U8, T::U8 )
OPCODE(SignedSaturatedSub16, T::U16, T::U16, T::U16 )
OPCODE(SignedSaturatedSub32, T::U32, T::U32, T::U32 )
OPCODE(SignedSaturatedSub64, T::U64, T::U64, T::U64 )
OPCODE(SignedSaturation, T::U32, T::U32, T::U8 )
OPCODE(UnsignedSaturation, T::U32, T::U32, T::U8 )
// Packed instructions
OPCODE(PackedAddU8, T::U32, T::U32, T::U32 )