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A64: Implement CLZ's vector variant

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This commit is contained in:
Lioncash
2018-09-09 17:46:21 -04:00
committed by MerryMage
parent e739624296
commit 112cff9ab9
2 changed files with 20 additions and 1 deletions
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src/frontend/A64/decoder/a64.inc
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@@ -616,7 +616,7 @@ INST(FRECPE_4, "FRECPE", "0Q001
INST(REV32_asimd, "REV32 (vector)", "0Q101110zz100000000010nnnnnddddd")
INST(UADDLP, "UADDLP", "0Q101110zz100000001010nnnnnddddd")
INST(USQADD_2, "USQADD", "0Q101110zz100000001110nnnnnddddd")
//INST(CLZ_asimd, "CLZ (vector)", "0Q101110zz100000010010nnnnnddddd")
INST(CLZ_asimd, "CLZ (vector)", "0Q101110zz100000010010nnnnnddddd")
INST(UADALP, "UADALP", "0Q101110zz100000011010nnnnnddddd")
INST(SQNEG_2, "SQNEG", "0Q101110zz100000011110nnnnnddddd")
INST(CMGE_zero_2, "CMGE (zero)", "0Q101110zz100000100010nnnnnddddd")