SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-06 02:26:30 +00:00
Code Issues Packages Projects Releases Wiki Activity

A64: Implement SRHADD and URHADD

Browse Source
This commit is contained in:
Lioncash
2018-05-23 17:35:30 -04:00
committed by MerryMage
parent bc718c5b28
commit 11a92eaaef
2 changed files with 31 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/frontend/A64/decoder/a64.inc
View File

@@ -703,7 +703,7 @@ INST(UMULL_vec, "UMULL, UMULL2 (vector)", "0Q101
// Data Processing - FP and SIMD - SIMD three same
INST(SHADD, "SHADD", "0Q001110zz1mmmmm000001nnnnnddddd")
//INST(SQADD_2, "SQADD", "0Q001110zz1mmmmm000011nnnnnddddd")
//INST(SRHADD, "SRHADD", "0Q001110zz1mmmmm000101nnnnnddddd")
INST(SRHADD, "SRHADD", "0Q001110zz1mmmmm000101nnnnnddddd")
INST(SHSUB, "SHSUB", "0Q001110zz1mmmmm001001nnnnnddddd")
//INST(SQSUB_2, "SQSUB", "0Q001110zz1mmmmm001011nnnnnddddd")
INST(CMGT_reg_2, "CMGT (register)", "0Q001110zz1mmmmm001101nnnnnddddd")
@@ -744,7 +744,7 @@ INST(ORR_asimd_reg, "ORR (vector, register)", "0Q001
INST(ORN_asimd, "ORN (vector)", "0Q001110111mmmmm000111nnnnnddddd")
INST(UHADD, "UHADD", "0Q101110zz1mmmmm000001nnnnnddddd")
//INST(UQADD_2, "UQADD", "0Q101110zz1mmmmm000011nnnnnddddd")
//INST(URHADD, "URHADD", "0Q101110zz1mmmmm000101nnnnnddddd")
INST(URHADD, "URHADD", "0Q101110zz1mmmmm000101nnnnnddddd")
INST(UHSUB, "UHSUB", "0Q101110zz1mmmmm001001nnnnnddddd")
//INST(UQSUB_2, "UQSUB", "0Q101110zz1mmmmm001011nnnnnddddd")
INST(CMHI_2, "CMHI (register)", "0Q101110zz1mmmmm001101nnnnnddddd")