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Implement UADD8

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This commit is contained in:
MerryMage
2016-12-04 20:52:33 +00:00
parent 7cad6949e7
commit 1a1646d962
5 changed files with 77 additions and 10 deletions
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6
src/frontend/ir/ir_emitter.cpp
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@@ -324,6 +324,12 @@ Value IREmitter::ByteReverseDual(const Value& a) {
return Inst(Opcode::ByteReverseDual, {a});
}
IREmitter::ResultAndGE IREmitter::PackedAddU8(const Value& a, const Value& b) {
auto result = Inst(Opcode::PackedAddU8, {a, b});
auto ge = Inst(Opcode::GetGEFromOp, {result});
return {result, ge};
}
Value IREmitter::PackedHalvingAddU8(const Value& a, const Value& b) {
return Inst(Opcode::PackedHalvingAddU8, {a, b});
}

6
src/frontend/ir/ir_emitter.h
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@@ -49,6 +49,11 @@ public:
Value overflow;
};
struct ResultAndGE {
Value result;
Value ge;
};
void Unimplemented();
u32 PC();
u32 AlignPC(size_t alignment);
@@ -122,6 +127,7 @@ public:
Value ByteReverseWord(const Value& a);
Value ByteReverseHalf(const Value& a);
Value ByteReverseDual(const Value& a);
ResultAndGE PackedAddU8(const Value& a, const Value& b);
Value PackedHalvingAddU8(const Value& a, const Value& b);
Value PackedHalvingAddS8(const Value& a, const Value& b);
Value PackedHalvingSubU8(const Value& a, const Value& b);

1
src/frontend/ir/opcodes.inc
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@@ -72,6 +72,7 @@ OPCODE(ZeroExtendByteToWord, T::U32, T::U8
OPCODE(ByteReverseWord, T::U32, T::U32 )
OPCODE(ByteReverseHalf, T::U16, T::U16 )
OPCODE(ByteReverseDual, T::U64, T::U64 )
OPCODE(PackedAddU8, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddU8, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddS8, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubU8, T::U32, T::U32, T::U32 )

9
src/frontend/translate/translate_arm/parallel.cpp
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@@ -35,7 +35,14 @@ bool ArmTranslatorVisitor::arm_SSUB16(Cond cond, Reg n, Reg d, Reg m) {
}
bool ArmTranslatorVisitor::arm_UADD8(Cond cond, Reg n, Reg d, Reg m) {
return InterpretThisInstruction();
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto result = ir.PackedAddU8(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result.result);
ir.SetGEFlags(result.ge);
}
return true;
}
bool ArmTranslatorVisitor::arm_UADD16(Cond cond, Reg n, Reg d, Reg m) {