SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-26 12:48:41 +00:00
Code Issues Packages Projects Releases Wiki Activity

A64: Implement FMAXNM (scalar)

Browse Source
This commit is contained in:
MerryMage
2018-02-20 14:05:14 +00:00
parent 1dfce0894d
commit 1c9804ea07
6 changed files with 123 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/frontend/A64/decoder/a64.inc
View File

@@ -927,7 +927,7 @@ INST(FADD_float, "FADD (scalar)", "00011
INST(FSUB_float, "FSUB (scalar)", "00011110yy1mmmmm001110nnnnnddddd")
INST(FMAX_float, "FMAX (scalar)", "00011110yy1mmmmm010010nnnnnddddd")
INST(FMIN_float, "FMIN (scalar)", "00011110yy1mmmmm010110nnnnnddddd")
//INST(FMAXNM_float, "FMAXNM (scalar)", "00011110yy1mmmmm011010nnnnnddddd")
INST(FMAXNM_float, "FMAXNM (scalar)", "00011110yy1mmmmm011010nnnnnddddd")
//INST(FMINNM_float, "FMINNM (scalar)", "00011110yy1mmmmm011110nnnnnddddd")
INST(FNMUL_float, "FNMUL (scalar)", "00011110yy1mmmmm100010nnnnnddddd")

15
src/frontend/A64/translate/impl/floating_point_data_processing_two_register.cpp
View File

@@ -113,6 +113,21 @@ bool TranslatorVisitor::FMIN_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::FMAXNM_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) {
auto datasize = GetDataSize(type);
if (!datasize) {
return UnallocatedEncoding();
}
const IR::U32U64 operand1 = V_scalar(*datasize, Vn);
const IR::U32U64 operand2 = V_scalar(*datasize, Vm);
const IR::U32U64 result = ir.FPMaxNumeric(operand1, operand2, true);
V_scalar(*datasize, Vd, result);
return true;
}
bool TranslatorVisitor::FNMUL_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) {
auto datasize = GetDataSize(type);
if (!datasize) {

10
src/frontend/ir/ir_emitter.cpp
View File

@@ -1185,6 +1185,16 @@ U32U64 IREmitter::FPMax(const U32U64& a, const U32U64& b, bool fpscr_controlled)
}
}
U32U64 IREmitter::FPMaxNumeric(const U32U64& a, const U32U64& b, bool fpscr_controlled) {
ASSERT(fpscr_controlled);
ASSERT(a.GetType() == b.GetType());
if (a.GetType() == Type::U32) {
return Inst<U32>(Opcode::FPMaxNumeric32, a, b);
} else {
return Inst<U64>(Opcode::FPMaxNumeric64, a, b);
}
}
U32U64 IREmitter::FPMin(const U32U64& a, const U32U64& b, bool fpscr_controlled) {
ASSERT(fpscr_controlled);
ASSERT(a.GetType() == b.GetType());

1
src/frontend/ir/ir_emitter.h
View File

@@ -247,6 +247,7 @@ public:
NZCV FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan, bool fpscr_controlled);
U32U64 FPDiv(const U32U64& a, const U32U64& b, bool fpscr_controlled);
U32U64 FPMax(const U32U64& a, const U32U64& b, bool fpscr_controlled);
U32U64 FPMaxNumeric(const U32U64& a, const U32U64& b, bool fpscr_controlled);
U32U64 FPMin(const U32U64& a, const U32U64& b, bool fpscr_controlled);
U32U64 FPMul(const U32U64& a, const U32U64& b, bool fpscr_controlled);
U32U64 FPNeg(const U32U64& a);

2
src/frontend/ir/opcodes.inc
View File

@@ -300,6 +300,8 @@ OPCODE(FPDiv32, T::U32, T::U32, T::U32
OPCODE(FPDiv64, T::U64, T::U64, T::U64 )
OPCODE(FPMax32, T::U32, T::U32, T::U32 )
OPCODE(FPMax64, T::U64, T::U64, T::U64 )
OPCODE(FPMaxNumeric32, T::U32, T::U32, T::U32 )
OPCODE(FPMaxNumeric64, T::U64, T::U64, T::U64 )
OPCODE(FPMin32, T::U32, T::U32, T::U32 )
OPCODE(FPMin64, T::U64, T::U64, T::U64 )
OPCODE(FPMul32, T::U32, T::U32, T::U32 )