SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-02-18 22:42:58 +00:00
Code Issues Packages Projects Releases Wiki Activity

A64: Implement system register CTR_EL0

Browse Source
This commit is contained in:
MerryMage
2018-02-20 16:44:13 +00:00
parent 58fbb3ff1b
commit 1e15283d00
6 changed files with 22 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
include/dynarmic/A64/config.h
View File

@@ -103,6 +103,13 @@ struct UserConfig {
/// Executing DC ZVA in this mode will result in zeros being written to memory.
bool hook_data_cache_operations = false;
/// CTR_EL0<27:24> is log2 of the cache writeback granule in words.
/// CTR_EL0<23:20> is log2 of the exclusives reservation granule in words.
/// CTR_EL0<19:16> is log2 of the smallest data/unifed cacheline in words.
/// CTR_EL0<15:14> is the level 1 instruction cache policy.
/// CTR_EL0<3:0> is log2 of the smallest instruction cacheline in words.
std::uint32_t ctr_el0 = 0x8444c004;
/// DCZID_EL0<3:0> is log2 of the block size in words
/// DCZID_EL0<4> is 0 if the DC ZVA instruction is permitted.
std::uint32_t dczid_el0 = 4;