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https://git.suyu.dev/suyu/dynarmic.git
synced 2026-03-08 09:46:27 +00:00
thumb32: Implement SHSUB8/UHSUB8
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@@ -252,7 +252,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
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INST(&V::thumb32_SHSAX, "SHSAX", "111110101110nnnn1111dddd0010mmmm"),
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INST(&V::thumb32_SHSUB16, "SHSUB16", "111110101101nnnn1111dddd0010mmmm"),
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INST(&V::thumb32_SHADD8, "SHADD8", "111110101000nnnn1111dddd0010mmmm"),
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//INST(&V::thumb32_SHSUB8, "SHSUB8", "111110101100----1111----0010----"),
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INST(&V::thumb32_SHSUB8, "SHSUB8", "111110101100nnnn1111dddd0010mmmm"),
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// Parallel Addition and Subtraction (unsigned)
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INST(&V::thumb32_UADD16, "UADD16", "111110101001nnnn1111dddd0100mmmm"),
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@@ -272,7 +272,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
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INST(&V::thumb32_UHSAX, "UHSAX", "111110101110nnnn1111dddd0110mmmm"),
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INST(&V::thumb32_UHSUB16, "UHSUB16", "111110101101nnnn1111dddd0110mmmm"),
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INST(&V::thumb32_UHADD8, "UHADD8", "111110101000nnnn1111dddd0110mmmm"),
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//INST(&V::thumb32_UHSUB8, "UHSUB8", "111110101100----1111----0110----"),
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INST(&V::thumb32_UHSUB8, "UHSUB8", "111110101100nnnn1111dddd0110mmmm"),
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// Miscellaneous Operations
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INST(&V::thumb32_QADD, "QADD", "111110101000nnnn1111dddd1000mmmm"),
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@@ -414,6 +414,19 @@ bool ThumbTranslatorVisitor::thumb32_SHSAX(Reg n, Reg d, Reg m) {
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_SHSUB8(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto reg_m = ir.GetRegister(m);
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const auto reg_n = ir.GetRegister(n);
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const auto result = ir.PackedHalvingSubS8(reg_n, reg_m);
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ir.SetRegister(d, result);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_SHSUB16(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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@@ -479,6 +492,19 @@ bool ThumbTranslatorVisitor::thumb32_UHSAX(Reg n, Reg d, Reg m) {
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_UHSUB8(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto reg_m = ir.GetRegister(m);
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const auto reg_n = ir.GetRegister(n);
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const auto result = ir.PackedHalvingSubU8(reg_n, reg_m);
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ir.SetRegister(d, result);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_UHSUB16(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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@@ -159,11 +159,13 @@ struct ThumbTranslatorVisitor final {
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bool thumb32_SHADD16(Reg n, Reg d, Reg m);
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bool thumb32_SHASX(Reg n, Reg d, Reg m);
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bool thumb32_SHSAX(Reg n, Reg d, Reg m);
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bool thumb32_SHSUB8(Reg n, Reg d, Reg m);
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bool thumb32_SHSUB16(Reg n, Reg d, Reg m);
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bool thumb32_UHADD8(Reg n, Reg d, Reg m);
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bool thumb32_UHADD16(Reg n, Reg d, Reg m);
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bool thumb32_UHASX(Reg n, Reg d, Reg m);
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bool thumb32_UHSAX(Reg n, Reg d, Reg m);
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bool thumb32_UHSUB8(Reg n, Reg d, Reg m);
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bool thumb32_UHSUB16(Reg n, Reg d, Reg m);
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};
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