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A32: Implement ARM-mode BFI

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This commit is contained in:
Lioncash
2019-04-20 11:57:58 -04:00
committed by MerryMage
parent fab3a59e05
commit 2970b34e3c
5 changed files with 32 additions and 3 deletions
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1
src/frontend/A32/decoder/arm.inc
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@@ -165,6 +165,7 @@ INST(arm_STM_usr, "STM (usr reg)", "----100--100--------------------
// Miscellaneous instructions
INST(arm_BFC, "BFC", "cccc0111110vvvvvddddvvvvv0011111") // v6T2
INST(arm_BFI, "BFI", "cccc0111110vvvvvddddvvvvv001nnnn") // v6T2
INST(arm_CLZ, "CLZ", "cccc000101101111dddd11110001mmmm") // v5
INST(arm_NOP, "NOP", "----0011001000001111000000000000") // v6K
INST(arm_SEL, "SEL", "cccc01101000nnnndddd11111011mmmm") // v6

3
src/frontend/A32/disassembler/disassembler_arm.cpp
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@@ -586,6 +586,9 @@ public:
std::string arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) {
return fmt::format("bfc{} {}, #{}, #{}", CondToString(cond), d, lsb, msb - lsb + 1);
}
std::string arm_BFI(Cond cond, Imm5 msb, Reg d, Imm5 lsb, Reg n) {
return fmt::format("bfi{} {}, {}, #{}, #{}", CondToString(cond), d, n, lsb, msb - lsb + 1);
}
std::string arm_CLZ(Cond cond, Reg d, Reg m) {
return fmt::format("clz{} {}, {}", CondToString(cond), d, m);
}

23
src/frontend/A32/translate/translate_arm/misc.cpp
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@@ -30,6 +30,29 @@ bool ArmTranslatorVisitor::arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) {
return true;
}
// BFI<c> <Rd>, <Rn>, #<lsb>, #<width>
bool ArmTranslatorVisitor::arm_BFI(Cond cond, Imm5 msb, Reg d, Imm5 lsb, Reg n) {
if (d == Reg::PC) {
return UnpredictableInstruction();
}
if (msb < lsb) {
return UnpredictableInstruction();
}
if (!ConditionPassed(cond)) {
return true;
}
const u32 inclusion_mask = Common::Ones<u32>(msb - lsb + 1) << lsb;
const u32 exclusion_mask = ~inclusion_mask;
const IR::U32 operand1 = ir.And(ir.GetRegister(d), ir.Imm32(exclusion_mask));
const IR::U32 operand2 = ir.And(ir.LogicalShiftLeft(ir.GetRegister(n), ir.Imm8(lsb)), ir.Imm32(inclusion_mask));
const IR::U32 result = ir.Or(operand1, operand2);
ir.SetRegister(d, result);
return true;
}
// CLZ<c> <Rd>, <Rm>
bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) {
if (d == Reg::PC || m == Reg::PC) {

1
src/frontend/A32/translate/translate_arm/translate_arm.h
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@@ -208,6 +208,7 @@ struct ArmTranslatorVisitor final {
// Miscellaneous instructions
bool arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb);
bool arm_BFI(Cond cond, Imm5 msb, Reg d, Imm5 lsb, Reg n);
bool arm_CLZ(Cond cond, Reg d, Reg m);
bool arm_NOP() { return true; }
bool arm_RBIT(Cond cond, Reg d, Reg m);