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IR: Implement VectorExtract, VectorExtractLower IR instructions
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@@ -872,6 +872,16 @@ U128 IREmitter::VectorEqual(size_t esize, const U128& a, const U128& b) {
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return {};
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}
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U128 IREmitter::VectorExtract(const U128& a, const U128& b, size_t position) {
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ASSERT(position <= 128);
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return Inst<U128>(Opcode::VectorExtract, a, b, Imm8(static_cast<u8>(position)));
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}
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U128 IREmitter::VectorExtractLower(const U128& a, const U128& b, size_t position) {
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ASSERT(position <= 64);
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return Inst<U128>(Opcode::VectorExtractLower, a, b, Imm8(static_cast<u8>(position)));
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}
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U128 IREmitter::VectorGreaterSigned(size_t esize, const U128& a, const U128& b) {
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switch (esize) {
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case 8:
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@@ -215,6 +215,8 @@ public:
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U128 VectorBroadcastLower(size_t esize, const UAny& a);
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U128 VectorEor(const U128& a, const U128& b);
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U128 VectorEqual(size_t esize, const U128& a, const U128& b);
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U128 VectorExtract(const U128& a, const U128& b, size_t position);
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U128 VectorExtractLower(const U128& a, const U128& b, size_t position);
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U128 VectorGreaterEqualSigned(size_t esize, const U128& a, const U128& b);
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U128 VectorGreaterEqualUnsigned(size_t esize, const U128& a, const U128& b);
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U128 VectorGreaterSigned(size_t esize, const U128& a, const U128& b);
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@@ -233,6 +233,8 @@ OPCODE(VectorEqual16, T::U128, T::U128, T::U
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OPCODE(VectorEqual32, T::U128, T::U128, T::U128 )
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OPCODE(VectorEqual64, T::U128, T::U128, T::U128 )
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OPCODE(VectorEqual128, T::U128, T::U128, T::U128 )
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OPCODE(VectorExtract, T::U128, T::U128, T::U128, T::U8 )
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OPCODE(VectorExtractLower, T::U128, T::U128, T::U128, T::U8 )
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OPCODE(VectorGreaterS8, T::U128, T::U128, T::U128 )
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OPCODE(VectorGreaterS16, T::U128, T::U128, T::U128 )
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OPCODE(VectorGreaterS32, T::U128, T::U128, T::U128 )
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