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A64: Implement SQSHL (register)'s scalar variant

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We can implement this in terms of the vector variant.
This commit is contained in:
Lioncash
2019-03-04 14:15:02 -05:00
committed by MerryMage
parent 36027ebef5
commit 35ddf68ad5
2 changed files with 12 additions and 1 deletions
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src/frontend/A64/decoder/a64.inc
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@@ -490,7 +490,7 @@ INST(SQSUB_1, "SQSUB", "01011
INST(CMGT_reg_1, "CMGT (register)", "01011110zz1mmmmm001101nnnnnddddd")
INST(CMGE_reg_1, "CMGE (register)", "01011110zz1mmmmm001111nnnnnddddd")
INST(SSHL_1, "SSHL", "01011110zz1mmmmm010001nnnnnddddd")
//INST(SQSHL_reg_1, "SQSHL (register)", "01011110zz1mmmmm010011nnnnnddddd")
INST(SQSHL_reg_1, "SQSHL (register)", "01011110zz1mmmmm010011nnnnnddddd")
INST(SRSHL_1, "SRSHL", "01011110zz1mmmmm010101nnnnnddddd")
//INST(SQRSHL_1, "SQRSHL", "01011110zz1mmmmm010111nnnnnddddd")
INST(ADD_1, "ADD (vector)", "01011110zz1mmmmm100001nnnnnddddd")