SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-05 18:22:57 +00:00
Code Issues Packages Projects Releases Wiki Activity

A64: Implement SQXTN (vector)

Browse Source
This commit is contained in:
MerryMage
2018-07-24 17:59:14 +01:00
parent 8ef114d48f
commit 3874cb37e3
8 changed files with 139 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/frontend/A64/decoder/a64.inc
View File

@@ -579,7 +579,7 @@ INST(CMEQ_zero_2, "CMEQ (zero)", "0Q001
INST(CMLT_2, "CMLT (zero)", "0Q001110zz100000101010nnnnnddddd")
INST(ABS_2, "ABS", "0Q001110zz100000101110nnnnnddddd")
INST(XTN, "XTN, XTN2", "0Q001110zz100001001010nnnnnddddd")
//INST(SQXTN_2, "SQXTN, SQXTN2", "0Q001110zz100001010010nnnnnddddd")
INST(SQXTN_2, "SQXTN, SQXTN2", "0Q001110zz100001010010nnnnnddddd")
//INST(FCVTN, "FCVTN, FCVTN2", "0Q0011100z100001011010nnnnnddddd")
//INST(FCVTL, "FCVTL, FCVTL2", "0Q0011100z100001011110nnnnnddddd")
//INST(FRINTN_1, "FRINTN (vector)", "0Q00111001111001100010nnnnnddddd")

72
src/frontend/A64/translate/impl/impl.h
View File

@@ -515,35 +515,20 @@ struct TranslatorVisitor final {
// Data Processing - FP and SIMD - Scalar two-register misc
bool SUQADD_1(Imm<2> size, Vec Vn, Vec Vd);
bool SUQADD_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool SQABS_1(Imm<2> size, Vec Vn, Vec Vd);
bool SQABS_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool CMGT_zero_1(Imm<2> size, Vec Vn, Vec Vd);
bool CMGT_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool CMEQ_zero_1(Imm<2> size, Vec Vn, Vec Vd);
bool CMEQ_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool CMLT_1(Imm<2> size, Vec Vn, Vec Vd);
bool CMLT_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool ABS_1(Imm<2> size, Vec Vn, Vec Vd);
bool ABS_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool SQXTN_1(Imm<2> size, Vec Vn, Reg Rd);
bool SQXTN_2(bool Q, Imm<2> size, Vec Vn, Reg Rd);
bool USQADD_1(Imm<2> size, Vec Vn, Vec Vd);
bool USQADD_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool SQNEG_1(Imm<2> size, Vec Vn, Vec Vd);
bool SQNEG_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool CMGE_zero_1(Imm<2> size, Vec Vn, Vec Vd);
bool CMGE_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool CMLE_1(Imm<2> size, Vec Vn, Vec Vd);
bool CMLE_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool NEG_1(Imm<2> size, Vec Vn, Vec Vd);
bool NEG_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool SQXTUN_1(Imm<2> size, Vec Vn, Reg Rd);
bool SQXTUN_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool UQXTN_1(Imm<2> size, Vec Vn, Reg Rd);
bool UQXTN_2(bool Q, Imm<2> size, Vec Vn, Reg Rd);
bool FCVTXN_1(bool sz, Vec Vn, Reg Rd);
bool FCVTXN_2(bool Q, bool sz, Vec Vn, Reg Rd);
// Data Processing - FP and SIMD - SIMD Scalar pairwise
bool ADDP_pair(Imm<2> size, Vec Vn, Vec Vd);
@@ -704,28 +689,6 @@ struct TranslatorVisitor final {
bool FMINNMP_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
bool FMINP_vec_1(bool Q, Vec Vm, Vec Vn, Vec Vd);
// Data Processing - FP and SIMD - SIMD Two-register misc
bool FRINTN_1(bool Q, Vec Vn, Vec Vd);
bool FRINTN_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FRINTM_1(bool Q, Vec Vn, Vec Vd);
bool FRINTM_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FABS_1(bool Q, Vec Vn, Vec Vd);
bool FABS_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FRINTP_1(bool Q, Vec Vn, Vec Vd);
bool FRINTP_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FRINTZ_1(bool Q, Vec Vn, Vec Vd);
bool FRINTZ_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FRINTA_1(bool Q, Vec Vn, Vec Vd);
bool FRINTA_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FRINTX_1(bool Q, Vec Vn, Vec Vd);
bool FRINTX_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FNEG_1(bool Q, Vec Vn, Vec Vd);
bool FNEG_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FRINTI_1(bool Q, Vec Vn, Vec Vd);
bool FRINTI_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FSQRT_1(bool Q, Vec Vn, Vec Vd);
bool FSQRT_2(bool Q, bool sz, Vec Vn, Vec Vd);
// Data Processing - FP and SIMD - SIMD Three same extra
bool SDOT_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
bool UDOT_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
@@ -751,6 +714,41 @@ struct TranslatorVisitor final {
bool NOT(bool Q, Vec Vn, Vec Vd);
bool RBIT_asimd(bool Q, Vec Vn, Vec Vd);
bool URSQRTE(bool Q, bool sz, Vec Vn, Vec Vd);
bool SUQADD_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool SQABS_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool CMGT_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool CMEQ_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool CMLT_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool ABS_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool SQXTN_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool USQADD_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool SQNEG_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool CMGE_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool CMLE_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool NEG_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool SQXTUN_2(bool Q, Imm<2> size, Vec Vn, Vec Vd);
bool UQXTN_2(bool Q, Imm<2> size, Vec Vn, Reg Rd);
bool FCVTXN_2(bool Q, bool sz, Vec Vn, Reg Rd);
bool FRINTN_1(bool Q, Vec Vn, Vec Vd);
bool FRINTN_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FRINTM_1(bool Q, Vec Vn, Vec Vd);
bool FRINTM_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FABS_1(bool Q, Vec Vn, Vec Vd);
bool FABS_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FRINTP_1(bool Q, Vec Vn, Vec Vd);
bool FRINTP_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FRINTZ_1(bool Q, Vec Vn, Vec Vd);
bool FRINTZ_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FRINTA_1(bool Q, Vec Vn, Vec Vd);
bool FRINTA_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FRINTX_1(bool Q, Vec Vn, Vec Vd);
bool FRINTX_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FNEG_1(bool Q, Vec Vn, Vec Vd);
bool FNEG_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FRINTI_1(bool Q, Vec Vn, Vec Vd);
bool FRINTI_2(bool Q, bool sz, Vec Vn, Vec Vd);
bool FSQRT_1(bool Q, Vec Vn, Vec Vd);
bool FSQRT_2(bool Q, bool sz, Vec Vn, Vec Vd);
// Data Processing - FP and SIMD - SIMD across lanes
bool SADDLV(bool Q, Imm<2> size, Vec Vn, Vec Vd);

16
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
View File

@@ -291,6 +291,22 @@ bool TranslatorVisitor::SQXTUN_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::SQXTN_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend<size_t>();
const size_t datasize = 64;
const size_t part = Q ? 1 : 0;
const IR::U128 operand = V(2 * datasize, Vn);
const IR::U128 result = ir.VectorSignedSaturatedNarrowToSigned(2 * esize, operand);
Vpart(datasize, Vd, part, result);
return true;
}
bool TranslatorVisitor::NOT(bool Q, Vec Vn, Vec Vd) {
const size_t datasize = Q ? 128 : 64;