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A32: Implement VFPv3 VCT (between floating-point and fixed-point)

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This commit is contained in:
MerryMage
2020-06-22 21:03:20 +01:00
parent 48b2ffdde9
commit 3ea49fc6d6
9 changed files with 322 additions and 54 deletions
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4
src/frontend/A32/decoder/vfp.inc
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@@ -30,10 +30,10 @@ INST(vfp_VRINTR, "VRINTR", "cccc11101D110110dddd101z0
INST(vfp_VRINTZ, "VRINTZ", "cccc11101D110110dddd101z11M0mmmm") // VFPv5
INST(vfp_VCVT_f_to_f, "VCVT (f32<->f64)", "cccc11101D110111dddd101z11M0mmmm") // VFPv2
INST(vfp_VCVT_from_int, "VCVT (from int)", "cccc11101D111000dddd101zs1M0mmmm") // VFPv2
//INST(vfp_VCVT_from_fixed, "VCVT (from fixed)", "cccc11101D11101Udddd101zx1i0vvvv") // VFPv3
INST(vfp_VCVT_from_fixed, "VCVT (from fixed)", "cccc11101D11101Udddd101zx1i0vvvv") // VFPv3
INST(vfp_VCVT_to_u32, "VCVT (to u32)", "cccc11101D111100dddd101zr1M0mmmm") // VFPv2
INST(vfp_VCVT_to_s32, "VCVT (to s32)", "cccc11101D111101dddd101zr1M0mmmm") // VFPv2
//INST(vfp_VCVT_to_fixed, "VCVT (to fixed)", "cccc11101D11111Udddd101zx1i0vvvv") // VFPv3
INST(vfp_VCVT_to_fixed, "VCVT (to fixed)", "cccc11101D11111Udddd101zx1i0vvvv") // VFPv3
INST(vfp_VRINT_rm, "VRINT{A,N,P,M}", "111111101D1110mmdddd101z01M0mmmm") // VFPv5
INST(vfp_VCVT_rm, "VCVT{A,N,P,M}", "111111101D1111mmdddd101zU1M0mmmm") // VFPv5

12
src/frontend/A32/disassembler/disassembler_arm.cpp
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@@ -1436,6 +1436,12 @@ public:
return fmt::format("vcvt{}.{}.{} {}, {}", CondToString(cond), sz ? "f64" : "f32", is_signed ? "s32" : "u32", FPRegStr(sz, Vd, D), FPRegStr(false, Vm, M));
}
std::string vfp_VCVT_from_fixed(Cond cond, bool D, bool U, size_t Vd, bool sz, bool sx, Imm<1> i, Imm<4> imm4) {
const size_t size = sx ? 32 : 16;
const size_t fbits = size - concatenate(imm4, i).ZeroExtend();
return fmt::format("vcvt{}.{}.{}{} {}, {}, #{}", CondToString(cond), sz ? "f64" : "f32", U ? 'u' : 's', size, FPRegStr(sz, Vd, D), FPRegStr(sz, Vd, D), fbits);
}
std::string vfp_VCVT_to_u32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm) {
return fmt::format("vcvt{}{}.u32.{} {}, {}", round_towards_zero ? "" : "r", CondToString(cond), sz ? "f64" : "f32", FPRegStr(false, Vd, D), FPRegStr(sz, Vm, M));
}
@@ -1444,6 +1450,12 @@ public:
return fmt::format("vcvt{}{}.s32.{} {}, {}", round_towards_zero ? "" : "r", CondToString(cond), sz ? "f64" : "f32", FPRegStr(false, Vd, D), FPRegStr(sz, Vm, M));
}
std::string vfp_VCVT_to_fixed(Cond cond, bool D, bool U, size_t Vd, bool sz, bool sx, Imm<1> i, Imm<4> imm4) {
const size_t size = sx ? 32 : 16;
const size_t fbits = size - concatenate(imm4, i).ZeroExtend();
return fmt::format("vcvt{}.{}{}.{} {}, {}, #{}", CondToString(cond), U ? 'u' : 's', size, sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vd, D), fbits);
}
std::string vfp_VRINT_rm(bool D, size_t rm, size_t Vd, bool sz, bool M, size_t Vm) {
return fmt::format("vrint{}.{} {}, {}", "anpm"[rm], sz ? "f64" : "f32", FPRegStr(sz, Vd, D), FPRegStr(sz, Vm, M));
}

2
src/frontend/A32/translate/impl/translate_arm.h
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@@ -427,8 +427,10 @@ struct ArmTranslatorVisitor final {
bool vfp_VRINTZ(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
bool vfp_VCVT_f_to_f(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
bool vfp_VCVT_from_int(Cond cond, bool D, size_t Vd, bool sz, bool is_signed, bool M, size_t Vm);
bool vfp_VCVT_from_fixed(Cond cond, bool D, bool U, size_t Vd, bool sz, bool sx, Imm<1> i, Imm<4> imm4);
bool vfp_VCVT_to_u32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm);
bool vfp_VCVT_to_s32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm);
bool vfp_VCVT_to_fixed(Cond cond, bool D, bool U, size_t Vd, bool sz, bool sx, Imm<1> i, Imm<4> imm4);
bool vfp_VRINT_rm(bool D, size_t rm, size_t Vd, bool sz, bool M, size_t Vm);
bool vfp_VCVT_rm(bool D, size_t rm, size_t Vd, bool sz, bool U, bool M, size_t Vm);

68
src/frontend/A32/translate/impl/vfp.cpp
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@@ -966,6 +966,38 @@ bool ArmTranslatorVisitor::vfp_VCVT_from_int(Cond cond, bool D, size_t Vd, bool
return true;
}
// VCVT.F32.{S16,U16,S32,U32} <Sdm>, <Sdm>
// VCVT.F64.{S16,U16,S32,U32} <Ddm>, <Ddm>
bool ArmTranslatorVisitor::vfp_VCVT_from_fixed(Cond cond, bool D, bool U, size_t Vd, bool sz, bool sx, Imm<1> i, Imm<4> imm4) {
if (!ConditionPassed(cond)) {
return true;
}
const size_t size = sx ? 32 : 16;
const size_t fbits = size - concatenate(imm4, i).ZeroExtend();
if (fbits > size) {
return UnpredictableInstruction();
}
const auto d = ToExtReg(sz, Vd, D);
const auto rounding_mode = FP::RoundingMode::ToNearest_TieEven;
const auto reg_d = ir.GetExtendedRegister(d);
const auto source = ir.LeastSignificant(size, reg_d);
if (sz) {
const auto result = U ? ir.FPUnsignedFixedToDouble(source, fbits, rounding_mode)
: ir.FPSignedFixedToDouble(source, fbits, rounding_mode);
ir.SetExtendedRegister(d, result);
} else {
const auto result = U ? ir.FPUnsignedFixedToSingle(source, fbits, rounding_mode)
: ir.FPSignedFixedToSingle(source, fbits, rounding_mode);
ir.SetExtendedRegister(d, result);
}
return true;
}
// VCVT{,R}.U32.F32 <Sd>, <Sm>
// VCVT{,R}.U32.F64 <Sd>, <Dm>
bool ArmTranslatorVisitor::vfp_VCVT_to_u32(Cond cond, bool D, size_t Vd, bool sz, bool round_towards_zero, bool M, size_t Vm) {
@@ -998,6 +1030,42 @@ bool ArmTranslatorVisitor::vfp_VCVT_to_s32(Cond cond, bool D, size_t Vd, bool sz
return true;
}
// VCVT.{S16,U16,S32,U32}.F32 <Sdm>, <Sdm>
// VCVT.{S16,U16,S32,U32}.F64 <Ddm>, <Ddm>
bool ArmTranslatorVisitor::vfp_VCVT_to_fixed(Cond cond, bool D, bool U, size_t Vd, bool sz, bool sx, Imm<1> i, Imm<4> imm4) {
if (!ConditionPassed(cond)) {
return true;
}
const size_t size = sx ? 32 : 16;
const size_t fbits = size - concatenate(imm4, i).ZeroExtend();
if (fbits > size) {
return UnpredictableInstruction();
}
const auto d = ToExtReg(sz, Vd, D);
const auto rounding_mode = FP::RoundingMode::TowardsZero;
const auto reg_d = ir.GetExtendedRegister(d);
const auto result = [&]() -> IR::U16U32U64 {
if (sx) {
return U ? ir.FPToFixedU32(reg_d, fbits, rounding_mode)
: ir.FPToFixedS32(reg_d, fbits, rounding_mode);
} else {
return U ? ir.FPToFixedU16(reg_d, fbits, rounding_mode)
: ir.FPToFixedS16(reg_d, fbits, rounding_mode);
}
}();
if (sz) {
ir.SetExtendedRegister(d, U ? ir.ZeroExtendToLong(result) : ir.SignExtendToLong(result));
} else {
ir.SetExtendedRegister(d, U ? ir.ZeroExtendToWord(result) : ir.SignExtendToWord(result));
}
return true;
}
// VRINT{A,N,P,M}.F32 <Sd>, <Sm>
// VRINT{A,N,P,M}.F64 <Dd>, <Dm>
bool ArmTranslatorVisitor::vfp_VRINT_rm(bool D, size_t rm, size_t Vd, bool sz, bool M, size_t Vm) {