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A64: Implement SIMD instruction USRA, vector variant

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MerryMage
2018-02-10 11:12:54 +00:00
parent fb9d20f27f
commit 3f93c77ace
2 changed files with 22 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@@ -792,7 +792,7 @@ INST(SHL_2, "SHL", "0Q001
//INST(SCVTF_fix_2, "SCVTF (vector, fixed-point)", "0Q0011110IIIIiii111001nnnnnddddd")
//INST(FCVTZS_fix_2, "FCVTZS (vector, fixed-point)", "0Q0011110IIIIiii111111nnnnnddddd")
INST(USHR_2, "USHR", "0Q1011110IIIIiii000001nnnnnddddd")
//INST(USRA_2, "USRA", "0Q1011110IIIIiii000101nnnnnddddd")
INST(USRA_2, "USRA", "0Q1011110IIIIiii000101nnnnnddddd")
//INST(URSHR_2, "URSHR", "0Q1011110IIIIiii001001nnnnnddddd")
//INST(URSRA_2, "URSRA", "0Q1011110IIIIiii001101nnnnnddddd")
//INST(SRI_2, "SRI", "0Q1011110IIIIiii010001nnnnnddddd")