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IR: Merge U32 and U64 variants of FP instructions
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@@ -869,78 +869,78 @@ U128 IREmitter::VectorZeroUpper(const U128& a) {
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return Inst<U128>(Opcode::VectorZeroUpper, a);
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}
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U32 IREmitter::FPAbs32(const U32& a) {
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return Inst<U32>(Opcode::FPAbs32, a);
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U32U64 IREmitter::FPAbs(const U32U64& a) {
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if (a.GetType() == Type::U32) {
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return Inst<U32>(Opcode::FPAbs32, a);
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} else {
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return Inst<U64>(Opcode::FPAbs64, a);
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}
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}
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U64 IREmitter::FPAbs64(const U64& a) {
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return Inst<U64>(Opcode::FPAbs64, a);
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}
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U32 IREmitter::FPAdd32(const U32& a, const U32& b, bool fpscr_controlled) {
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U32U64 IREmitter::FPAdd(const U32U64& a, const U32U64& b, bool fpscr_controlled) {
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ASSERT(fpscr_controlled);
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return Inst<U32>(Opcode::FPAdd32, a, b);
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ASSERT(a.GetType() == b.GetType());
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if (a.GetType() == Type::U32) {
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return Inst<U32>(Opcode::FPAdd32, a, b);
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} else {
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return Inst<U64>(Opcode::FPAdd64, a, b);
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}
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}
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U64 IREmitter::FPAdd64(const U64& a, const U64& b, bool fpscr_controlled) {
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void IREmitter::FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan, bool fpscr_controlled) {
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ASSERT(fpscr_controlled);
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return Inst<U64>(Opcode::FPAdd64, a, b);
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ASSERT(a.GetType() == b.GetType());
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if (a.GetType() == Type::U32) {
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Inst(Opcode::FPCompare32, a, b, Imm1(exc_on_qnan));
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} else {
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Inst(Opcode::FPCompare64, a, b, Imm1(exc_on_qnan));
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}
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}
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void IREmitter::FPCompare32(const U32& a, const U32& b, bool exc_on_qnan, bool fpscr_controlled) {
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U32U64 IREmitter::FPDiv(const U32U64& a, const U32U64& b, bool fpscr_controlled) {
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ASSERT(fpscr_controlled);
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Inst(Opcode::FPCompare32, a, b, Imm1(exc_on_qnan));
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ASSERT(a.GetType() == b.GetType());
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if (a.GetType() == Type::U32) {
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return Inst<U32>(Opcode::FPDiv32, a, b);
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} else {
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return Inst<U64>(Opcode::FPDiv64, a, b);
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}
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}
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void IREmitter::FPCompare64(const U64& a, const U64& b, bool exc_on_qnan, bool fpscr_controlled) {
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U32U64 IREmitter::FPMul(const U32U64& a, const U32U64& b, bool fpscr_controlled) {
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ASSERT(fpscr_controlled);
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Inst(Opcode::FPCompare64, a, b, Imm1(exc_on_qnan));
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ASSERT(a.GetType() == b.GetType());
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if (a.GetType() == Type::U32) {
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return Inst<U32>(Opcode::FPMul32, a, b);
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} else {
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return Inst<U64>(Opcode::FPMul64, a, b);
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}
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}
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U32 IREmitter::FPDiv32(const U32& a, const U32& b, bool fpscr_controlled) {
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U32U64 IREmitter::FPNeg(const U32U64& a) {
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if (a.GetType() == Type::U32) {
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return Inst<U32>(Opcode::FPNeg32, a);
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} else {
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return Inst<U64>(Opcode::FPNeg64, a);
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}
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}
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U32U64 IREmitter::FPSqrt(const U32U64& a) {
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if (a.GetType() == Type::U32) {
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return Inst<U32>(Opcode::FPSqrt32, a);
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} else {
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return Inst<U64>(Opcode::FPSqrt64, a);
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}
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}
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U32U64 IREmitter::FPSub(const U32U64& a, const U32U64& b, bool fpscr_controlled) {
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ASSERT(fpscr_controlled);
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return Inst<U32>(Opcode::FPDiv32, a, b);
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}
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U64 IREmitter::FPDiv64(const U64& a, const U64& b, bool fpscr_controlled) {
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ASSERT(fpscr_controlled);
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return Inst<U64>(Opcode::FPDiv64, a, b);
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}
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U32 IREmitter::FPMul32(const U32& a, const U32& b, bool fpscr_controlled) {
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ASSERT(fpscr_controlled);
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return Inst<U32>(Opcode::FPMul32, a, b);
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}
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U64 IREmitter::FPMul64(const U64& a, const U64& b, bool fpscr_controlled) {
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ASSERT(fpscr_controlled);
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return Inst<U64>(Opcode::FPMul64, a, b);
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}
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U32 IREmitter::FPNeg32(const U32& a) {
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return Inst<U32>(Opcode::FPNeg32, a);
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}
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U64 IREmitter::FPNeg64(const U64& a) {
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return Inst<U64>(Opcode::FPNeg64, a);
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}
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U32 IREmitter::FPSqrt32(const U32& a) {
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return Inst<U32>(Opcode::FPSqrt32, a);
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}
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U64 IREmitter::FPSqrt64(const U64& a) {
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return Inst<U64>(Opcode::FPSqrt64, a);
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}
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U32 IREmitter::FPSub32(const U32& a, const U32& b, bool fpscr_controlled) {
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ASSERT(fpscr_controlled);
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return Inst<U32>(Opcode::FPSub32, a, b);
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}
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U64 IREmitter::FPSub64(const U64& a, const U64& b, bool fpscr_controlled) {
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ASSERT(fpscr_controlled);
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return Inst<U64>(Opcode::FPSub64, a, b);
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ASSERT(a.GetType() == b.GetType());
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if (a.GetType() == Type::U32) {
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return Inst<U32>(Opcode::FPSub32, a, b);
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} else {
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return Inst<U64>(Opcode::FPSub64, a, b);
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}
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}
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U32 IREmitter::FPDoubleToSingle(const U64& a, bool fpscr_controlled) {
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