SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-06 18:36:30 +00:00
Code Issues Packages Projects Releases Wiki Activity

A64: Implement FRSQRTE (vector), single/double variant

Browse Source
This commit is contained in:
MerryMage
2018-07-23 22:46:12 +01:00
parent b74d5520f9
commit 45dc5f74f3
6 changed files with 75 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/frontend/A64/decoder/a64.inc
View File

@@ -654,7 +654,7 @@ INST(FCMLE_4, "FCMLE (zero)", "0Q101
//INST(FCVTZU_int_4, "FCVTZU (vector, integer)", "0Q1011101z100001101110nnnnnddddd")
//INST(URSQRTE, "URSQRTE", "0Q1011101z100001110010nnnnnddddd")
//INST(FRSQRTE_3, "FRSQRTE", "0Q10111011111001110110nnnnnddddd")
//INST(FRSQRTE_4, "FRSQRTE", "0Q1011101z100001110110nnnnnddddd")
INST(FRSQRTE_4, "FRSQRTE", "0Q1011101z100001110110nnnnnddddd")
//INST(FSQRT_1, "FSQRT (vector)", "0Q10111011111001111110nnnnnddddd")
//INST(FSQRT_2, "FSQRT (vector)", "0Q1011101z100001111110nnnnnddddd")

15
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
View File

@@ -217,6 +217,21 @@ bool TranslatorVisitor::FCMLT_4(bool Q, bool sz, Vec Vn, Vec Vd) {
return FPCompareAgainstZero(*this, Q, sz, Vn, Vd, ComparisonType::LT);
}
bool TranslatorVisitor::FRSQRTE_4(bool Q, bool sz, Vec Vn, Vec Vd) {
if (sz && !Q) {
return ReservedValue();
}
const size_t datasize = Q ? 128 : 64;
const size_t esize = sz ? 64 : 32;
const IR::U128 operand = V(datasize, Vn);
const IR::U128 result = ir.FPVectorRSqrtEstimate(esize, operand);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::FNEG_1(bool Q, Vec Vn, Vec Vd) {
const size_t datasize = Q ? 128 : 64;

11
src/frontend/ir/ir_emitter.cpp
View File

@@ -1679,6 +1679,17 @@ U128 IREmitter::FPVectorPairedAddLower(size_t esize, const U128& a, const U128&
return {};
}
U128 IREmitter::FPVectorRSqrtEstimate(size_t esize, const U128& a) {
switch (esize) {
case 32:
return Inst<U128>(Opcode::FPVectorRSqrtEstimate32, a);
case 64:
return Inst<U128>(Opcode::FPVectorRSqrtEstimate64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorSub(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 32:

1
src/frontend/ir/ir_emitter.h
View File

@@ -299,6 +299,7 @@ public:
U128 FPVectorMul(size_t esize, const U128& a, const U128& b);
U128 FPVectorPairedAdd(size_t esize, const U128& a, const U128& b);
U128 FPVectorPairedAddLower(size_t esize, const U128& a, const U128& b);
U128 FPVectorRSqrtEstimate(size_t esize, const U128& a);
U128 FPVectorSub(size_t esize, const U128& a, const U128& b);
U128 FPVectorS32ToSingle(const U128& a);
U128 FPVectorS64ToDouble(const U128& a);

2
src/frontend/ir/opcodes.inc
View File

@@ -435,6 +435,8 @@ OPCODE(FPVectorPairedAddLower32, T::U128, T::U128, T::U
OPCODE(FPVectorPairedAddLower64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorPairedAdd32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorPairedAdd64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorRSqrtEstimate32, T::U128, T::U128 )
OPCODE(FPVectorRSqrtEstimate64, T::U128, T::U128 )
OPCODE(FPVectorS32ToSingle, T::U128, T::U128 )
OPCODE(FPVectorS64ToDouble, T::U128, T::U128 )
OPCODE(FPVectorSub32, T::U128, T::U128, T::U128 )