SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-06 18:36:30 +00:00
Code Issues Packages Projects Releases Wiki Activity

A32: Implement ASIMD VQMOVUN, VQMOVN

Browse Source
This commit is contained in:
MerryMage
2020-06-22 20:02:52 +01:00
parent 52b8039367
commit 48b2ffdde9
3 changed files with 35 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
View File

@@ -564,6 +564,37 @@ bool ArmTranslatorVisitor::asimd_VMOVN(bool D, size_t sz, size_t Vd, bool M, siz
return true;
}
bool ArmTranslatorVisitor::asimd_VQMOVUN(bool D, size_t sz, size_t Vd, bool M, size_t Vm) {
if (sz == 0b11 || Common::Bit<0>(Vm)) {
return UndefinedInstruction();
}
const size_t esize = 8U << sz;
const auto d = ToVector(false, Vd, D);
const auto m = ToVector(true, Vm, M);
const auto reg_m = ir.GetVector(m);
const auto result = ir.VectorSignedSaturatedNarrowToUnsigned(2 * esize, reg_m);
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VQMOVN(bool D, size_t sz, size_t Vd, bool op, bool M, size_t Vm) {
if (sz == 0b11 || Common::Bit<0>(Vm)) {
return UndefinedInstruction();
}
const size_t esize = 8U << sz;
const auto d = ToVector(false, Vd, D);
const auto m = ToVector(true, Vm, M);
const auto reg_m = ir.GetVector(m);
const auto result = op ? ir.VectorUnsignedSaturatedNarrow(2 * esize, reg_m)
: ir.VectorSignedSaturatedNarrowToSigned(2 * esize, reg_m);
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();

2
src/frontend/A32/translate/impl/translate_arm.h
View File

@@ -552,6 +552,8 @@ struct ArmTranslatorVisitor final {
bool asimd_VUZP(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);
bool asimd_VZIP(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);
bool asimd_VMOVN(bool D, size_t sz, size_t Vd, bool M, size_t Vm);
bool asimd_VQMOVUN(bool D, size_t sz, size_t Vd, bool M, size_t Vm);
bool asimd_VQMOVN(bool D, size_t sz, size_t Vd, bool op, bool M, size_t Vm);
bool asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);
bool asimd_VRSQRTE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);
bool asimd_VCVT_integer(bool D, size_t sz, size_t Vd, bool op, bool U, bool Q, bool M, size_t Vm);