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TranslateArm: Implement QADD8 and UQADD8.
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@@ -61,7 +61,11 @@ bool ArmTranslatorVisitor::arm_USUB16(Cond cond, Reg n, Reg d, Reg m) {
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// Parallel Add/Subtract (Saturating) instructions
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bool ArmTranslatorVisitor::arm_QADD8(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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if (ConditionPassed(cond)) {
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auto result = ir.PackedSaturatedAddS8(ir.GetRegister(n), ir.GetRegister(m));
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ir.SetRegister(d, result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_QADD16(Cond cond, Reg n, Reg d, Reg m) {
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@@ -89,7 +93,11 @@ bool ArmTranslatorVisitor::arm_QSUB16(Cond cond, Reg n, Reg d, Reg m) {
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}
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bool ArmTranslatorVisitor::arm_UQADD8(Cond cond, Reg n, Reg d, Reg m) {
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return InterpretThisInstruction();
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if (ConditionPassed(cond)) {
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auto result = ir.PackedSaturatedAddU8(ir.GetRegister(n), ir.GetRegister(m));
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ir.SetRegister(d, result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_UQADD16(Cond cond, Reg n, Reg d, Reg m) {
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