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A64: Implement ADD (vector), scalar variant

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MerryMage
2018-02-06 22:09:39 +00:00
parent 2a0850c068
commit 4c5871d5d5
3 changed files with 28 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@@ -494,7 +494,7 @@ INST(AESIMC, "AESIMC", "01001
//INST(SQSHL_reg_1, "SQSHL (register)", "01011110zz1mmmmm010011nnnnnddddd")
//INST(SRSHL_1, "SRSHL", "01011110zz1mmmmm010101nnnnnddddd")
//INST(SQRSHL_1, "SQRSHL", "01011110zz1mmmmm010111nnnnnddddd")
//INST(ADD_1, "ADD (vector)", "01011110zz1mmmmm100001nnnnnddddd")
INST(ADD_1, "ADD (vector)", "01011110zz1mmmmm100001nnnnnddddd")
//INST(CMTST_1, "CMTST", "01011110zz1mmmmm100011nnnnnddddd")
//INST(SQDMULH_vec_1, "SQDMULH (vector)", "01011110zz1mmmmm101101nnnnnddddd")
//INST(UQADD_1, "UQADD", "01111110zz1mmmmm000011nnnnnddddd")