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A64: Implement ASRV, LSLV, LSRV, and RORV

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Lioncash
2018-01-21 22:28:24 -05:00
committed by MerryMage
parent a8a65beb2b
commit 4d8f4aa8af
3 changed files with 71 additions and 4 deletions
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8
src/frontend/A64/decoder/a64.inc
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@@ -276,10 +276,10 @@ INST(UnallocatedEncoding, "", "10111
// Data Processing - Register - 2 source
//INST(UDIV, "UDIV", "z0011010110mmmmm000010nnnnnddddd")
//INST(SDIV, "SDIV", "z0011010110mmmmm000011nnnnnddddd")
//INST(LSLV, "LSLV", "z0011010110mmmmm001000nnnnnddddd")
//INST(LSRV, "LSRV", "z0011010110mmmmm001001nnnnnddddd")
//INST(ASRV, "ASRV", "z0011010110mmmmm001010nnnnnddddd")
//INST(RORV, "RORV", "z0011010110mmmmm001011nnnnnddddd")
INST(LSLV, "LSLV", "z0011010110mmmmm001000nnnnnddddd")
INST(LSRV, "LSRV", "z0011010110mmmmm001001nnnnnddddd")
INST(ASRV, "ASRV", "z0011010110mmmmm001010nnnnnddddd")
INST(RORV, "RORV", "z0011010110mmmmm001011nnnnnddddd")
//INST(CRC32, "CRC32B, CRC32H, CRC32W, CRC32X", "z0011010110mmmmm0100zznnnnnddddd")
//INST(CRC32C, "CRC32CB, CRC32CH, CRC32CW, CRC32CX", "z0011010110mmmmm0101zznnnnnddddd")
//INST(PACGA, "PACGA", "10011010110mmmmm001100nnnnnddddd")