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https://git.suyu.dev/suyu/dynarmic.git
synced 2026-03-14 13:26:28 +00:00
Implemented UMULH and SMULH instructions
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@@ -299,10 +299,10 @@ INST(MADD, "MADD", "z0011
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INST(MSUB, "MSUB", "z0011011000mmmmm1aaaaannnnnddddd")
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INST(SMADDL, "SMADDL", "10011011001mmmmm0aaaaannnnnddddd")
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INST(SMSUBL, "SMSUBL", "10011011001mmmmm1aaaaannnnnddddd")
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//INST(SMULH, "SMULH", "10011011010mmmmm011111nnnnnddddd")
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INST(SMULH, "SMULH", "10011011010mmmmm011111nnnnnddddd")
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INST(UMADDL, "UMADDL", "10011011101mmmmm0aaaaannnnnddddd")
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INST(UMSUBL, "UMSUBL", "10011011101mmmmm1aaaaannnnnddddd")
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//INST(UMULH, "UMULH", "10011011110mmmmm011111nnnnnddddd")
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INST(UMULH, "UMULH", "10011011110mmmmm011111nnnnnddddd")
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// Data Processing - FP and SIMD - AES
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INST(AESE, "AESE", "0100111000101000010010nnnnnddddd")
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@@ -56,6 +56,16 @@ bool TranslatorVisitor::SMSUBL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
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return true;
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}
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bool TranslatorVisitor::SMULH(Reg Rm, Reg Rn, Reg Rd) {
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const IR::U64 m = X(64, Rm);
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const IR::U64 n = X(64, Rn);
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const IR::U64 result = ir.SignedMultiplyHigh(n, m);
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X(64, Rd, result);
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return true;
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}
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bool TranslatorVisitor::UMADDL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
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const IR::U64 a = X(64, Ra);
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const IR::U64 m = ir.ZeroExtendToLong(X(32, Rm));
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@@ -78,6 +88,16 @@ bool TranslatorVisitor::UMSUBL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
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return true;
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}
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bool TranslatorVisitor::UMULH(Reg Rm, Reg Rn, Reg Rd) {
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const IR::U64 m = X(64, Rm);
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const IR::U64 n = X(64, Rn);
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const IR::U64 result = ir.UnsignedMultiplyHigh(n, m);
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X(64, Rd, result);
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return true;
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}
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bool TranslatorVisitor::UDIV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
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const size_t datasize = sf ? 64 : 32;
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@@ -280,6 +280,14 @@ U32U64 IREmitter::Mul(const U32U64& a, const U32U64& b) {
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return Inst<U64>(Opcode::Mul64, a, b);
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}
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U64 IREmitter::UnsignedMultiplyHigh(const U64& a, const U64& b) {
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return Inst<U64>(Opcode::UnsignedMultiplyHigh64, a, b);
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}
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U64 IREmitter::SignedMultiplyHigh(const U64& a, const U64& b) {
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return Inst<U64>(Opcode::SignedMultiplyHigh64, a, b);
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}
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U32 IREmitter::UnsignedDiv(const U32& a, const U32& b) {
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return Inst<U32>(Opcode::UnsignedDiv32, a, b);
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}
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@@ -112,6 +112,8 @@ public:
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U32 Mul(const U32& a, const U32& b);
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U64 Mul(const U64& a, const U64& b);
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U32U64 Mul(const U32U64& a, const U32U64& b);
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U64 UnsignedMultiplyHigh(const U64& a, const U64& b);
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U64 SignedMultiplyHigh(const U64& a, const U64& b);
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U32 UnsignedDiv(const U32& a, const U32& b);
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U64 UnsignedDiv(const U64& a, const U64& b);
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U32U64 UnsignedDiv(const U32U64& a, const U32U64& b);
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@@ -98,6 +98,8 @@ OPCODE(Sub32, T::U32, T::U32, T::U32,
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OPCODE(Sub64, T::U64, T::U64, T::U64, T::U1 )
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OPCODE(Mul32, T::U32, T::U32, T::U32 )
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OPCODE(Mul64, T::U64, T::U64, T::U64 )
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OPCODE(SignedMultiplyHigh64, T::U64, T::U64, T::U64 )
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OPCODE(UnsignedMultiplyHigh64, T::U64, T::U64, T::U64 )
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OPCODE(UnsignedDiv32, T::U32, T::U32, T::U32 )
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OPCODE(UnsignedDiv64, T::U64, T::U64, T::U64 )
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OPCODE(SignedDiv32, T::U32, T::U32, T::U32 )
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