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A64: Implement load/store single structure instructions

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Implements LD{1, 2, 3, 4}, LD{1, 2, 3, 4}R, and ST{1, 2, 3, 4} single
structure variants.
This commit is contained in:
Lioncash
2018-07-04 14:05:53 -04:00
committed by MerryMage
parent b6e223fc58
commit 593eca7fb1
4 changed files with 256 additions and 40 deletions
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32
src/frontend/A64/translate/impl/impl.h
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@@ -182,26 +182,26 @@ struct TranslatorVisitor final {
bool LDx_mult_2(bool Q, Reg Rm, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt);
// Loads and stores - Advanced SIMD Load/Store single structures
bool ST1_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool ST1_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool ST3_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool ST3_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool ST2_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool ST2_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool ST4_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool ST4_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool LD1_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool LD1_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool LD3_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool LD3_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool ST1_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool ST1_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool ST3_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool ST3_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool ST2_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool ST2_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool ST4_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool ST4_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool LD1_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool LD1_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool LD3_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool LD3_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool LD1R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt);
bool LD1R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt);
bool LD3R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt);
bool LD3R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt);
bool LD2_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool LD2_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool LD4_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool LD4_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool LD2_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool LD2_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool LD4_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool LD4_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
bool LD2R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt);
bool LD2R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt);
bool LD4R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt);