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IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128

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ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
This commit is contained in:
MerryMage
2018-01-19 01:09:46 +00:00
parent 9a812b0c61
commit 5eb0bdecdf
10 changed files with 150 additions and 226 deletions
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8
src/frontend/A32/ir_emitter.cpp
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@@ -30,13 +30,13 @@ IR::U32 IREmitter::GetRegister(Reg reg) {
return Inst<IR::U32>(Opcode::A32GetRegister, IR::Value(reg));
}
IR::F32F64 IREmitter::GetExtendedRegister(ExtReg reg) {
IR::U32U64 IREmitter::GetExtendedRegister(ExtReg reg) {
if (A32::IsSingleExtReg(reg)) {
return Inst<IR::F32F64>(Opcode::A32GetExtendedRegister32, IR::Value(reg));
return Inst<IR::U32U64>(Opcode::A32GetExtendedRegister32, IR::Value(reg));
}
if (A32::IsDoubleExtReg(reg)) {
return Inst<IR::F32F64>(Opcode::A32GetExtendedRegister64, IR::Value(reg));
return Inst<IR::U32U64>(Opcode::A32GetExtendedRegister64, IR::Value(reg));
}
ASSERT_MSG(false, "Invalid reg.");
@@ -47,7 +47,7 @@ void IREmitter::SetRegister(const Reg reg, const IR::U32& value) {
Inst(Opcode::A32SetRegister, IR::Value(reg), value);
}
void IREmitter::SetExtendedRegister(const ExtReg reg, const IR::F32F64& value) {
void IREmitter::SetExtendedRegister(const ExtReg reg, const IR::U32U64& value) {
if (A32::IsSingleExtReg(reg)) {
Inst(Opcode::A32SetExtendedRegister32, IR::Value(reg), value);
} else if (A32::IsDoubleExtReg(reg)) {