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Implement DC instructions

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This commit is contained in:
MerryMage
2018-02-11 22:53:46 +00:00
parent a9153218bd
commit 5edd623b9d
18 changed files with 218 additions and 33 deletions
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28
src/frontend/A64/translate/impl/branch.cpp
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@@ -12,8 +12,8 @@ bool TranslatorVisitor::B_cond(Imm<19> imm19, Cond cond) {
s64 offset = concatenate(imm19, Imm<2>{0}).SignExtend<s64>();
u64 target = ir.PC() + offset;
auto cond_pass = IR::Term::LinkBlock{ir.current_location.SetPC(target)};
auto cond_fail = IR::Term::LinkBlock{ir.current_location.AdvancePC(4)};
auto cond_pass = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
auto cond_fail = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
ir.SetTerm(IR::Term::If{cond, cond_pass, cond_fail});
return false;
}
@@ -22,7 +22,7 @@ bool TranslatorVisitor::B_uncond(Imm<26> imm26) {
s64 offset = concatenate(imm26, Imm<2>{0}).SignExtend<s64>();
u64 target = ir.PC() + offset;
ir.SetTerm(IR::Term::LinkBlock{ir.current_location.SetPC(target)});
ir.SetTerm(IR::Term::LinkBlock{ir.current_location->SetPC(target)});
return false;
}
@@ -30,10 +30,10 @@ bool TranslatorVisitor::BL(Imm<26> imm26) {
s64 offset = concatenate(imm26, Imm<2>{0}).SignExtend<s64>();
X(64, Reg::R30, ir.Imm64(ir.PC() + 4));
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.PushRSB(ir.current_location->AdvancePC(4));
u64 target = ir.PC() + offset;
ir.SetTerm(IR::Term::LinkBlock{ir.current_location.SetPC(target)});
ir.SetTerm(IR::Term::LinkBlock{ir.current_location->SetPC(target)});
return false;
}
@@ -41,7 +41,7 @@ bool TranslatorVisitor::BLR(Reg Rn) {
auto target = X(64, Rn);
X(64, Reg::R30, ir.Imm64(ir.PC() + 4));
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.PushRSB(ir.current_location->AdvancePC(4));
ir.SetPC(target);
ir.SetTerm(IR::Term::ReturnToDispatch{});
@@ -73,8 +73,8 @@ bool TranslatorVisitor::CBZ(bool sf, Imm<19> imm19, Reg Rt) {
ir.SetCheckBit(ir.IsZero(operand1));
u64 target = ir.PC() + offset;
auto cond_pass = IR::Term::LinkBlock{ir.current_location.SetPC(target)};
auto cond_fail = IR::Term::LinkBlock{ir.current_location.AdvancePC(4)};
auto cond_pass = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
auto cond_fail = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
ir.SetTerm(IR::Term::CheckBit{cond_pass, cond_fail});
return false;
}
@@ -88,8 +88,8 @@ bool TranslatorVisitor::CBNZ(bool sf, Imm<19> imm19, Reg Rt) {
ir.SetCheckBit(ir.IsZero(operand1));
u64 target = ir.PC() + offset;
auto cond_pass = IR::Term::LinkBlock{ir.current_location.AdvancePC(4)};
auto cond_fail = IR::Term::LinkBlock{ir.current_location.SetPC(target)};
auto cond_pass = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
auto cond_fail = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
ir.SetTerm(IR::Term::CheckBit{cond_pass, cond_fail});
return false;
}
@@ -104,8 +104,8 @@ bool TranslatorVisitor::TBZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) {
ir.SetCheckBit(ir.TestBit(operand, ir.Imm8(bit_pos)));
u64 target = ir.PC() + offset;
auto cond_1 = IR::Term::LinkBlock{ir.current_location.AdvancePC(4)};
auto cond_0 = IR::Term::LinkBlock{ir.current_location.SetPC(target)};
auto cond_1 = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
auto cond_0 = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
ir.SetTerm(IR::Term::CheckBit{cond_1, cond_0});
return false;
}
@@ -120,8 +120,8 @@ bool TranslatorVisitor::TBNZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) {
ir.SetCheckBit(ir.TestBit(operand, ir.Imm8(bit_pos)));
u64 target = ir.PC() + offset;
auto cond_1 = IR::Term::LinkBlock{ir.current_location.SetPC(target)};
auto cond_0 = IR::Term::LinkBlock{ir.current_location.AdvancePC(4)};
auto cond_1 = IR::Term::LinkBlock{ir.current_location->SetPC(target)};
auto cond_0 = IR::Term::LinkBlock{ir.current_location->AdvancePC(4)};
ir.SetTerm(IR::Term::CheckBit{cond_1, cond_0});
return false;
}