VFP: Implement {Get,Set}ExtendedRegister{32,64}

This commit is contained in:
MerryMage
2016-08-05 18:54:19 +01:00
parent d31bbd6d14
commit 640ce48baa
15 changed files with 262 additions and 16 deletions

View File

@@ -43,11 +43,31 @@ IR::Value IREmitter::GetRegister(Reg reg) {
return Inst(IR::Opcode::GetRegister, { IR::Value(reg) });
}
IR::Value IREmitter::GetExtendedRegister(ExtReg reg) {
if (reg >= Arm::ExtReg::S0 && reg <= Arm::ExtReg::S31) {
return Inst(IR::Opcode::GetExtendedRegister32, {IR::Value(reg)});
} else if (reg >= Arm::ExtReg::D0 && reg <= Arm::ExtReg::D31) {
return Inst(IR::Opcode::GetExtendedRegister64, {IR::Value(reg)});
} else {
ASSERT_MSG(false, "Invalid reg.");
}
}
void IREmitter::SetRegister(const Reg reg, const IR::Value& value) {
ASSERT(reg != Reg::PC);
Inst(IR::Opcode::SetRegister, { IR::Value(reg), value });
}
void IREmitter::SetExtendedRegister(const ExtReg reg, const IR::Value& value) {
if (reg >= Arm::ExtReg::S0 && reg <= Arm::ExtReg::S31) {
Inst(IR::Opcode::SetExtendedRegister32, {IR::Value(reg), value});
} else if (reg >= Arm::ExtReg::D0 && reg <= Arm::ExtReg::D31) {
Inst(IR::Opcode::SetExtendedRegister64, {IR::Value(reg), value});
} else {
ASSERT_MSG(false, "Invalid reg.");
}
}
void IREmitter::ALUWritePC(const IR::Value& value) {
// This behaviour is ARM version-dependent.
// The below implementation is for ARMv6k