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A32: Detect unpredictable LDM/STM instructions

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This commit is contained in:
MerryMage
2020-04-17 23:51:54 +01:00
parent cd1560c664
commit 668a43f815
5 changed files with 27 additions and 4 deletions
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12
src/frontend/A32/translate/impl/load_store.cpp
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@@ -768,6 +768,9 @@ bool ArmTranslatorVisitor::arm_LDM(Cond cond, bool W, Reg n, RegList list) {
if (n == Reg::PC || Common::BitCount(list) < 1) {
return UnpredictableInstruction();
}
if (W && Common::Bit(static_cast<size_t>(n), list)) {
return UnpredictableInstruction();
}
if (!ConditionPassed(cond)) {
return true;
@@ -783,6 +786,9 @@ bool ArmTranslatorVisitor::arm_LDMDA(Cond cond, bool W, Reg n, RegList list) {
if (n == Reg::PC || Common::BitCount(list) < 1) {
return UnpredictableInstruction();
}
if (W && Common::Bit(static_cast<size_t>(n), list)) {
return UnpredictableInstruction();
}
if (!ConditionPassed(cond)) {
return true;
@@ -798,6 +804,9 @@ bool ArmTranslatorVisitor::arm_LDMDB(Cond cond, bool W, Reg n, RegList list) {
if (n == Reg::PC || Common::BitCount(list) < 1) {
return UnpredictableInstruction();
}
if (W && Common::Bit(static_cast<size_t>(n), list)) {
return UnpredictableInstruction();
}
if (!ConditionPassed(cond)) {
return true;
@@ -813,6 +822,9 @@ bool ArmTranslatorVisitor::arm_LDMIB(Cond cond, bool W, Reg n, RegList list) {
if (n == Reg::PC || Common::BitCount(list) < 1) {
return UnpredictableInstruction();
}
if (W && Common::Bit(static_cast<size_t>(n), list)) {
return UnpredictableInstruction();
}
if (!ConditionPassed(cond)) {
return true;