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A32: Implement ASIMD VRECPE

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This commit is contained in:
MerryMage
2020-06-20 15:07:06 +01:00
parent d3dc50d718
commit 6f59c2cd8e
8 changed files with 47 additions and 18 deletions
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2
src/frontend/A32/decoder/asimd.inc
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@@ -103,7 +103,7 @@ INST(asimd_VSWP, "VSWP", "111100111D110010dddd000
//INST(asimd_VQMOVN, "VQMOVN", "111100111-11--10----00101x-0----") // ASIMD
//INST(asimd_VSHLL_max, "VSHLL_max", "111100111-11--10----001100-0----") // ASIMD
//INST(asimd_VCVT_half, "VCVT (half-precision)", "111100111-11--10----011x00-0----") // ASIMD
//INST(asimd_VRECPE, "VRECPE", "111100111-11--11----010x0x-0----") // ASIMD
INST(asimd_VRECPE, "VRECPE", "111100111D11zz11dddd010F0QM0mmmm") // ASIMD
//INST(asimd_VRSQRTE, "VRSQRTE", "111100111-11--11----010x1x-0----") // ASIMD
//INST(asimd_VCVT_integer, "VCVT (integer)", "111100111-11--11----011xxx-0----") // ASIMD

27
src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
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@@ -352,4 +352,31 @@ bool ArmTranslatorVisitor::asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t
return true;
}
bool ArmTranslatorVisitor::asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
if (sz == 0b00 || sz == 0b11) {
return UndefinedInstruction();
}
if (!F && sz == 0b01) {
// TODO: Implement 16-bit VectorUnsignedRecipEstimate
return UndefinedInstruction();
}
const size_t esize = 8U << sz;
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto reg_m = ir.GetVector(m);
const auto result = F ? ir.FPVectorRecipEstimate(esize, reg_m, false)
: ir.VectorUnsignedRecipEstimate(reg_m);
ir.SetVector(d, result);
return true;
}
} // namespace Dynarmic::A32

1
src/frontend/A32/translate/impl/translate_arm.h
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@@ -499,6 +499,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VABS(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);
bool asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);
bool asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm);
bool asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);
// Advanced SIMD load/store structures
bool v8_VST_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t sz, size_t align, Reg m);

8
src/frontend/ir/ir_emitter.cpp
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@@ -2440,14 +2440,14 @@ U128 IREmitter::FPVectorPairedAddLower(size_t esize, const U128& a, const U128&
UNREACHABLE();
}
U128 IREmitter::FPVectorRecipEstimate(size_t esize, const U128& a) {
U128 IREmitter::FPVectorRecipEstimate(size_t esize, const U128& a, bool fpcr_controlled) {
switch (esize) {
case 16:
return Inst<U128>(Opcode::FPVectorRecipEstimate16, a);
return Inst<U128>(Opcode::FPVectorRecipEstimate16, a, Imm1(fpcr_controlled));
case 32:
return Inst<U128>(Opcode::FPVectorRecipEstimate32, a);
return Inst<U128>(Opcode::FPVectorRecipEstimate32, a, Imm1(fpcr_controlled));
case 64:
return Inst<U128>(Opcode::FPVectorRecipEstimate64, a);
return Inst<U128>(Opcode::FPVectorRecipEstimate64, a, Imm1(fpcr_controlled));
}
UNREACHABLE();
}

2
src/frontend/ir/ir_emitter.h
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@@ -360,7 +360,7 @@ public:
U128 FPVectorNeg(size_t esize, const U128& a);
U128 FPVectorPairedAdd(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true);
U128 FPVectorPairedAddLower(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true);
U128 FPVectorRecipEstimate(size_t esize, const U128& a);
U128 FPVectorRecipEstimate(size_t esize, const U128& a, bool fpcr_controlled = true);
U128 FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true);
U128 FPVectorRoundInt(size_t esize, const U128& operand, FP::RoundingMode rounding, bool exact);
U128 FPVectorRSqrtEstimate(size_t esize, const U128& a);

6
src/frontend/ir/opcodes.inc
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@@ -613,9 +613,9 @@ OPCODE(FPVectorPairedAdd32, U128, U128
OPCODE(FPVectorPairedAdd64, U128, U128, U128, U1 )
OPCODE(FPVectorPairedAddLower32, U128, U128, U128, U1 )
OPCODE(FPVectorPairedAddLower64, U128, U128, U128, U1 )
OPCODE(FPVectorRecipEstimate16, U128, U128 )
OPCODE(FPVectorRecipEstimate32, U128, U128 )
OPCODE(FPVectorRecipEstimate64, U128, U128 )
OPCODE(FPVectorRecipEstimate16, U128, U128, U1 )
OPCODE(FPVectorRecipEstimate32, U128, U128, U1 )
OPCODE(FPVectorRecipEstimate64, U128, U128, U1 )
OPCODE(FPVectorRecipStepFused16, U128, U128, U128, U1 )
OPCODE(FPVectorRecipStepFused32, U128, U128, U128, U1 )
OPCODE(FPVectorRecipStepFused64, U128, U128, U128, U1 )