SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-06 02:26:30 +00:00
Code Issues Packages Projects Releases Wiki Activity

A32: Implement ASIMD VRECPE

Browse Source
This commit is contained in:
MerryMage
2020-06-20 15:07:06 +01:00
parent d3dc50d718
commit 6f59c2cd8e
8 changed files with 47 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/frontend/ir/ir_emitter.cpp
View File

@@ -2440,14 +2440,14 @@ U128 IREmitter::FPVectorPairedAddLower(size_t esize, const U128& a, const U128&
UNREACHABLE();
}
U128 IREmitter::FPVectorRecipEstimate(size_t esize, const U128& a) {
U128 IREmitter::FPVectorRecipEstimate(size_t esize, const U128& a, bool fpcr_controlled) {
switch (esize) {
case 16:
return Inst<U128>(Opcode::FPVectorRecipEstimate16, a);
return Inst<U128>(Opcode::FPVectorRecipEstimate16, a, Imm1(fpcr_controlled));
case 32:
return Inst<U128>(Opcode::FPVectorRecipEstimate32, a);
return Inst<U128>(Opcode::FPVectorRecipEstimate32, a, Imm1(fpcr_controlled));
case 64:
return Inst<U128>(Opcode::FPVectorRecipEstimate64, a);
return Inst<U128>(Opcode::FPVectorRecipEstimate64, a, Imm1(fpcr_controlled));
}
UNREACHABLE();
}

2
src/frontend/ir/ir_emitter.h
View File

@@ -360,7 +360,7 @@ public:
U128 FPVectorNeg(size_t esize, const U128& a);
U128 FPVectorPairedAdd(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true);
U128 FPVectorPairedAddLower(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true);
U128 FPVectorRecipEstimate(size_t esize, const U128& a);
U128 FPVectorRecipEstimate(size_t esize, const U128& a, bool fpcr_controlled = true);
U128 FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true);
U128 FPVectorRoundInt(size_t esize, const U128& operand, FP::RoundingMode rounding, bool exact);
U128 FPVectorRSqrtEstimate(size_t esize, const U128& a);

6
src/frontend/ir/opcodes.inc
View File

@@ -613,9 +613,9 @@ OPCODE(FPVectorPairedAdd32, U128, U128
OPCODE(FPVectorPairedAdd64, U128, U128, U128, U1 )
OPCODE(FPVectorPairedAddLower32, U128, U128, U128, U1 )
OPCODE(FPVectorPairedAddLower64, U128, U128, U128, U1 )
OPCODE(FPVectorRecipEstimate16, U128, U128 )
OPCODE(FPVectorRecipEstimate32, U128, U128 )
OPCODE(FPVectorRecipEstimate64, U128, U128 )
OPCODE(FPVectorRecipEstimate16, U128, U128, U1 )
OPCODE(FPVectorRecipEstimate32, U128, U128, U1 )
OPCODE(FPVectorRecipEstimate64, U128, U128, U1 )
OPCODE(FPVectorRecipStepFused16, U128, U128, U128, U1 )
OPCODE(FPVectorRecipStepFused32, U128, U128, U128, U1 )
OPCODE(FPVectorRecipStepFused64, U128, U128, U128, U1 )