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A64: Implement BIC (vector, register)

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MerryMage
2018-02-06 17:57:50 +00:00
parent ca43be4146
commit 7b33772ac6
2 changed files with 16 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@@ -791,7 +791,7 @@ INST(ADDP_vec, "ADDP (vector)", "0Q001
//INST(FMLAL_vec_1, "FMLAL, FMLAL2 (vector)", "0Q0011100z1mmmmm111011nnnnnddddd")
//INST(FMLAL_vec_2, "FMLAL, FMLAL2 (vector)", "0Q1011100z1mmmmm110011nnnnnddddd")
INST(AND_asimd, "AND (vector)", "0Q001110001mmmmm000111nnnnnddddd")
//INST(BIC_asimd_reg, "BIC (vector, register)", "0Q001110011mmmmm000111nnnnnddddd")
INST(BIC_asimd_reg, "BIC (vector, register)", "0Q001110011mmmmm000111nnnnnddddd")
//INST(FMLSL_vec_1, "FMLSL, FMLSL2 (vector)", "0Q0011101z1mmmmm111011nnnnnddddd")
//INST(FMLSL_vec_2, "FMLSL, FMLSL2 (vector)", "0Q1011101z1mmmmm110011nnnnnddddd")
INST(ORR_asimd_reg, "ORR (vector, register)", "0Q001110101mmmmm000111nnnnnddddd")