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A64: Implement FMAXNM and FMINNM vector variants.

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Currently we can implement these in terms of the scalar IR variants.
This commit is contained in:
Lioncash
2018-08-16 11:00:59 -04:00
committed by MerryMage
parent 8b65ea68c0
commit 7eb6be7a6a
2 changed files with 36 additions and 2 deletions
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4
src/frontend/A64/decoder/a64.inc
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@@ -724,7 +724,7 @@ INST(SMAXP, "SMAXP", "0Q001
INST(SMINP, "SMINP", "0Q001110zz1mmmmm101011nnnnnddddd")
//INST(SQDMULH_vec_2, "SQDMULH (vector)", "0Q001110zz1mmmmm101101nnnnnddddd")
INST(ADDP_vec, "ADDP (vector)", "0Q001110zz1mmmmm101111nnnnnddddd")
//INST(FMAXNM_2, "FMAXNM (vector)", "0Q0011100z1mmmmm110001nnnnnddddd")
INST(FMAXNM_2, "FMAXNM (vector)", "0Q0011100z1mmmmm110001nnnnnddddd")
INST(FMLA_vec_2, "FMLA (vector)", "0Q0011100z1mmmmm110011nnnnnddddd")
INST(FADD_2, "FADD (vector)", "0Q0011100z1mmmmm110101nnnnnddddd")
INST(FMAX_2, "FMAX (vector)", "0Q0011100z1mmmmm111101nnnnnddddd")
@@ -734,7 +734,7 @@ INST(FCMEQ_reg_4, "FCMEQ (register)", "0Q001
INST(FRECPS_4, "FRECPS", "0Q0011100z1mmmmm111111nnnnnddddd")
INST(AND_asimd, "AND (vector)", "0Q001110001mmmmm000111nnnnnddddd")
INST(BIC_asimd_reg, "BIC (vector, register)", "0Q001110011mmmmm000111nnnnnddddd")
//INST(FMINNM_2, "FMINNM (vector)", "0Q0011101z1mmmmm110001nnnnnddddd")
INST(FMINNM_2, "FMINNM (vector)", "0Q0011101z1mmmmm110001nnnnnddddd")
INST(FMLS_vec_2, "FMLS (vector)", "0Q0011101z1mmmmm110011nnnnnddddd")
INST(FSUB_2, "FSUB (vector)", "0Q0011101z1mmmmm110101nnnnnddddd")
//INST(FMLSL_vec_1, "FMLSL, FMLSL2 (vector)", "0Q0011101z1mmmmm111011nnnnnddddd")