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A64: Implement SQ{ADD, SUB}, and UQ{ADD, SUB}'s vector variants

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Currently we implement these in terms of the scalar variants. Falling
back to the interpreter is slow enough to make it more effective than
doing that.
This commit is contained in:
Lioncash
2018-08-13 14:50:29 -04:00
committed by MerryMage
parent a4b0e2ace6
commit 7ef7def661
2 changed files with 69 additions and 11 deletions
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8
src/frontend/A64/decoder/a64.inc
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@@ -702,10 +702,10 @@ INST(UMULL_vec, "UMULL, UMULL2 (vector)", "0Q101
// Data Processing - FP and SIMD - SIMD three same
INST(SHADD, "SHADD", "0Q001110zz1mmmmm000001nnnnnddddd")
//INST(SQADD_2, "SQADD", "0Q001110zz1mmmmm000011nnnnnddddd")
INST(SQADD_2, "SQADD", "0Q001110zz1mmmmm000011nnnnnddddd")
INST(SRHADD, "SRHADD", "0Q001110zz1mmmmm000101nnnnnddddd")
INST(SHSUB, "SHSUB", "0Q001110zz1mmmmm001001nnnnnddddd")
//INST(SQSUB_2, "SQSUB", "0Q001110zz1mmmmm001011nnnnnddddd")
INST(SQSUB_2, "SQSUB", "0Q001110zz1mmmmm001011nnnnnddddd")
INST(CMGT_reg_2, "CMGT (register)", "0Q001110zz1mmmmm001101nnnnnddddd")
INST(CMGE_reg_2, "CMGE (register)", "0Q001110zz1mmmmm001111nnnnnddddd")
INST(SSHL_2, "SSHL", "0Q001110zz1mmmmm010001nnnnnddddd")
@@ -743,10 +743,10 @@ INST(FRSQRTS_4, "FRSQRTS", "0Q001
INST(ORR_asimd_reg, "ORR (vector, register)", "0Q001110101mmmmm000111nnnnnddddd")
INST(ORN_asimd, "ORN (vector)", "0Q001110111mmmmm000111nnnnnddddd")
INST(UHADD, "UHADD", "0Q101110zz1mmmmm000001nnnnnddddd")
//INST(UQADD_2, "UQADD", "0Q101110zz1mmmmm000011nnnnnddddd")
INST(UQADD_2, "UQADD", "0Q101110zz1mmmmm000011nnnnnddddd")
INST(URHADD, "URHADD", "0Q101110zz1mmmmm000101nnnnnddddd")
INST(UHSUB, "UHSUB", "0Q101110zz1mmmmm001001nnnnnddddd")
//INST(UQSUB_2, "UQSUB", "0Q101110zz1mmmmm001011nnnnnddddd")
INST(UQSUB_2, "UQSUB", "0Q101110zz1mmmmm001011nnnnnddddd")
INST(CMHI_2, "CMHI (register)", "0Q101110zz1mmmmm001101nnnnnddddd")
INST(CMHS_2, "CMHS (register)", "0Q101110zz1mmmmm001111nnnnnddddd")
INST(USHL_2, "USHL", "0Q101110zz1mmmmm010001nnnnnddddd")