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A32: Implement barrier instructions introduced in ARMv7

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Provides basic implementations of the barrier instruction introduced
within ARMv7. Currently these simply mirror the behavior of the AArch64
equivalents.
This commit is contained in:
Lioncash
2019-04-26 16:41:41 -04:00
committed by MerryMage
parent 07218df353
commit 8316d231e9
11 changed files with 139 additions and 14 deletions
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41
src/frontend/ir/microinstruction.cpp
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@@ -45,6 +45,21 @@ bool Inst::IsShift() const {
IsLogicalShift();
}
bool Inst::IsBarrier() const {
switch (op) {
case Opcode::A32DataMemoryBarrier:
case Opcode::A32DataSynchronizationBarrier:
case Opcode::A32InstructionSynchronizationBarrier:
case Opcode::A64DataMemoryBarrier:
case Opcode::A64DataSynchronizationBarrier:
case Opcode::A64InstructionSynchronizationBarrier:
return true;
default:
return false;
}
}
bool Inst::IsSharedMemoryRead() const {
switch (op) {
case Opcode::A32ReadMemory8:
@@ -463,20 +478,18 @@ bool Inst::IsCoprocessorInstruction() const {
}
bool Inst::MayHaveSideEffects() const {
return op == Opcode::PushRSB ||
op == Opcode::A64SetCheckBit ||
op == Opcode::A64DataCacheOperationRaised ||
op == Opcode::A64DataSynchronizationBarrier ||
op == Opcode::A64DataMemoryBarrier ||
op == Opcode::A64InstructionSynchronizationBarrier ||
CausesCPUException() ||
WritesToCoreRegister() ||
WritesToSystemRegister() ||
WritesToCPSR() ||
WritesToFPCR() ||
WritesToFPSR() ||
AltersExclusiveState() ||
IsMemoryWrite() ||
return op == Opcode::PushRSB ||
op == Opcode::A64SetCheckBit ||
op == Opcode::A64DataCacheOperationRaised ||
IsBarrier() ||
CausesCPUException() ||
WritesToCoreRegister() ||
WritesToSystemRegister() ||
WritesToCPSR() ||
WritesToFPCR() ||
WritesToFPSR() ||
AltersExclusiveState() ||
IsMemoryWrite() ||
IsCoprocessorInstruction();
}