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general: Remove trailing spaces

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General code-related cleanup. Gets rid of trailing spaces in the
codebase.
This commit is contained in:
Lioncash
2019-05-04 21:03:30 -04:00
committed by MerryMage
parent fdbafbc1ae
commit 87083af733
35 changed files with 42 additions and 42 deletions
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2
src/frontend/A32/translate/translate_arm/vfp.cpp
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@@ -765,7 +765,7 @@ bool ArmTranslatorVisitor::vfp_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w
if (!p && !u && !w) {
ASSERT_MSG(false, "Decode error");
}
if (p && !w) {
ASSERT_MSG(false, "Decode error");
}

6
src/frontend/A64/translate/impl/data_processing_register.cpp
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@@ -34,17 +34,17 @@ bool TranslatorVisitor::RBIT_int(bool sf, Reg Rn, Reg Rd) {
const IR::U32 first_lsl = ir.LogicalShiftLeft(ir.And(operand, ir.Imm32(0x55555555)), ir.Imm8(1));
const IR::U32 first_lsr = ir.And(ir.LogicalShiftRight(operand, ir.Imm8(1)), ir.Imm32(0x55555555));
const IR::U32 first = ir.Or(first_lsl, first_lsr);
// x = (x & 0x33333333) << 2 | ((x >> 2) & 0x33333333);
const IR::U32 second_lsl = ir.LogicalShiftLeft(ir.And(first, ir.Imm32(0x33333333)), ir.Imm8(2));
const IR::U32 second_lsr = ir.And(ir.LogicalShiftRight(first, ir.Imm8(2)), ir.Imm32(0x33333333));
const IR::U32 second = ir.Or(second_lsl, second_lsr);
// x = (x & 0x0F0F0F0F) << 4 | ((x >> 4) & 0x0F0F0F0F);
const IR::U32 third_lsl = ir.LogicalShiftLeft(ir.And(second, ir.Imm32(0x0F0F0F0F)), ir.Imm8(4));
const IR::U32 third_lsr = ir.And(ir.LogicalShiftRight(second, ir.Imm8(4)), ir.Imm32(0x0F0F0F0F));
const IR::U32 third = ir.Or(third_lsl, third_lsr);
// x = (x << 24) | ((x & 0xFF00) << 8) | ((x >> 8) & 0xFF00) | (x >> 24);
const IR::U32 fourth_lsl = ir.Or(ir.LogicalShiftLeft(third, ir.Imm8(24)),
ir.LogicalShiftLeft(ir.And(third, ir.Imm32(0xFF00)), ir.Imm8(8)));

2
src/frontend/A64/translate/impl/load_store_register_register_offset.cpp
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@@ -67,7 +67,7 @@ static bool RegSharedDecodeAndOperation(TranslatorVisitor& v, size_t scale, u8 s
case MemOp::PREFETCH:
// TODO: Prefetch
break;
default:
default:
UNREACHABLE();
}

4
src/frontend/A64/translate/impl/simd_across_lanes.cpp
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@@ -89,7 +89,7 @@ bool FPMinMax(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd, MinMaxOpera
for (size_t i = start + 1; i < end; i++) {
const IR::U32U64 element = v.ir.VectorGetElement(esize, operand, i);
result = op(result, element);
}
@@ -128,7 +128,7 @@ bool ScalarMinMax(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd,
return v.ir.ZeroExtendToWord(vec_element);
};
const auto op_func = [&](const auto& a, const auto& b) {
switch (operation) {
case ScalarMinMaxOperation::Max:

2
src/frontend/A64/translate/impl/simd_sha512.cpp
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@@ -124,7 +124,7 @@ IR::U32 SM4Rotation(IREmitter& ir, IR::U32 intval, IR::U32 round_result_low_word
IR::U128 SM4Hash(IREmitter& ir, Vec Vn, Vec Vd, SM4RotationType type) {
const IR::U128 n = ir.GetQ(Vn);
IR::U128 roundresult = ir.GetQ(Vd);
for (size_t i = 0; i < 4; i++) {
const IR::U32 round_key = ir.VectorGetElement(32, n, i);

2
src/frontend/A64/translate/impl/simd_three_different.cpp
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@@ -90,7 +90,7 @@ enum class LongOperationBehavior {
Addition,
Subtraction
};
bool LongOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd,
LongOperationBehavior behavior, Signedness sign) {
if (size == 0b11) {

2
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
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@@ -99,7 +99,7 @@ bool IntegerConvertToFloat(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd
const IR::U128 operand = v.V(datasize, Vn);
const IR::U128 result = signedness == Signedness::Signed
? v.ir.FPVectorFromSignedFixed(esize, operand, 0, rounding_mode)
? v.ir.FPVectorFromSignedFixed(esize, operand, 0, rounding_mode)
: v.ir.FPVectorFromUnsignedFixed(esize, operand, 0, rounding_mode);
v.V(datasize, Vd, result);

2
src/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp
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@@ -96,7 +96,7 @@ bool FPMultiplyByElementHalfPrecision(TranslatorVisitor& v, bool Q, Imm<1> L, Im
const Vec Vm = Vmlo.ZeroExtend<Vec>();
const size_t esize = 16;
const size_t datasize = Q ? 128 : 64;
const IR::UAny element2 = v.ir.VectorGetElement(esize, v.V(idxdsize, Vm), index);
const IR::U128 operand1 = v.V(datasize, Vn);
const IR::U128 operand2 = Q ? v.ir.VectorBroadcast(esize, element2) : v.ir.VectorBroadcastLower(esize, element2);

4
src/frontend/A64/types.h
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@@ -20,7 +20,7 @@ using Cond = IR::Cond;
enum class Reg {
R0, R1, R2, R3, R4, R5, R6, R7,
R8, R9, R10, R11, R12, R13, R14, R15,
R8, R9, R10, R11, R12, R13, R14, R15,
R16, R17, R18, R19, R20, R21, R22, R23,
R24, R25, R26, R27, R28, R29, R30, R31,
LR = R30,
@@ -29,7 +29,7 @@ enum class Reg {
enum class Vec {
V0, V1, V2, V3, V4, V5, V6, V7,
V8, V9, V10, V11, V12, V13, V14, V15,
V8, V9, V10, V11, V12, V13, V14, V15,
V16, V17, V18, V19, V20, V21, V22, V23,
V24, V25, V26, V27, V28, V29, V30, V31,
};