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Standardize indentation of switch statments

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This commit is contained in:
MerryMage
2016-08-22 23:40:30 +01:00
parent 2471be317e
commit 8d1b9f32ca
12 changed files with 370 additions and 369 deletions
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56
src/frontend/disassembler/disassembler_arm.cpp
View File

@@ -35,18 +35,18 @@ public:
std::string ShiftStr(ShiftType shift, Imm5 imm5) {
switch (shift) {
case ShiftType::LSL:
if (imm5 == 0) return "";
return Common::StringFromFormat(", lsl #%hhu", imm5);
case ShiftType::LSR:
if (imm5 == 0) return ", lsr #32";
return Common::StringFromFormat(", lsr #%hhu", imm5);
case ShiftType::ASR:
if (imm5 == 0) return ", asr #32";
return Common::StringFromFormat(", asr #%hhu", imm5);
case ShiftType::ROR:
if (imm5 == 0) return ", rrx";
return Common::StringFromFormat(", ror #%hhu", imm5);
case ShiftType::LSL:
if (imm5 == 0) return "";
return Common::StringFromFormat(", lsl #%hhu", imm5);
case ShiftType::LSR:
if (imm5 == 0) return ", lsr #32";
return Common::StringFromFormat(", lsr #%hhu", imm5);
case ShiftType::ASR:
if (imm5 == 0) return ", asr #32";
return Common::StringFromFormat(", asr #%hhu", imm5);
case ShiftType::ROR:
if (imm5 == 0) return ", rrx";
return Common::StringFromFormat(", ror #%hhu", imm5);
}
ASSERT(false);
return "<internal error>";
@@ -54,14 +54,14 @@ public:
std::string RsrStr(Reg s, ShiftType shift, Reg m) {
switch (shift){
case ShiftType::LSL:
return Common::StringFromFormat("%s, lsl %s", RegToString(m), RegToString(s));
case ShiftType::LSR:
return Common::StringFromFormat("%s, lsr %s", RegToString(m), RegToString(s));
case ShiftType::ASR:
return Common::StringFromFormat("%s, asr %s", RegToString(m), RegToString(s));
case ShiftType::ROR:
return Common::StringFromFormat("%s, ror %s", RegToString(m), RegToString(s));
case ShiftType::LSL:
return Common::StringFromFormat("%s, lsl %s", RegToString(m), RegToString(s));
case ShiftType::LSR:
return Common::StringFromFormat("%s, lsr %s", RegToString(m), RegToString(s));
case ShiftType::ASR:
return Common::StringFromFormat("%s, asr %s", RegToString(m), RegToString(s));
case ShiftType::ROR:
return Common::StringFromFormat("%s, ror %s", RegToString(m), RegToString(s));
}
ASSERT(false);
return "<internal error>";
@@ -69,14 +69,14 @@ public:
std::string RorStr(Reg m, SignExtendRotation rotate) {
switch (rotate) {
case SignExtendRotation::ROR_0:
return RegToString(m);
case SignExtendRotation::ROR_8:
return Common::StringFromFormat("%s, ror #8", RegToString(m));
case SignExtendRotation::ROR_16:
return Common::StringFromFormat("%s, ror #16", RegToString(m));
case SignExtendRotation::ROR_24:
return Common::StringFromFormat("%s, ror #24", RegToString(m));
case SignExtendRotation::ROR_0:
return RegToString(m);
case SignExtendRotation::ROR_8:
return Common::StringFromFormat("%s, ror #8", RegToString(m));
case SignExtendRotation::ROR_16:
return Common::StringFromFormat("%s, ror #16", RegToString(m));
case SignExtendRotation::ROR_24:
return Common::StringFromFormat("%s, ror #24", RegToString(m));
}
ASSERT(false);
return "<internal error>";

24
src/frontend/ir/basic_block.cpp
View File

@@ -42,18 +42,18 @@ std::string DumpBlock(const IR::Block& block) {
return Common::StringFromFormat("%%%zu", inst_to_index.at(arg.GetInst()));
}
switch (arg.GetType()) {
case Type::U1:
return Common::StringFromFormat("#%s", arg.GetU1() ? "1" : "0");
case Type::U8:
return Common::StringFromFormat("#%u", arg.GetU8());
case Type::U32:
return Common::StringFromFormat("#%#x", arg.GetU32());
case Type::RegRef:
return Arm::RegToString(arg.GetRegRef());
case Type::ExtRegRef:
return Arm::ExtRegToString(arg.GetExtRegRef());
default:
return "<unknown immediate type>";
case Type::U1:
return Common::StringFromFormat("#%s", arg.GetU1() ? "1" : "0");
case Type::U8:
return Common::StringFromFormat("#%u", arg.GetU8());
case Type::U32:
return Common::StringFromFormat("#%#x", arg.GetU32());
case Type::RegRef:
return Arm::RegToString(arg.GetRegRef());
case Type::ExtRegRef:
return Arm::ExtRegToString(arg.GetExtRegRef());
default:
return "<unknown immediate type>";
}
};

32
src/frontend/ir/microinstruction.cpp
View File

@@ -259,14 +259,14 @@ void Inst::Use(Value& value) {
value.GetInst()->use_count++;
switch (op){
case Opcode::GetCarryFromOp:
value.GetInst()->carry_inst = this;
break;
case Opcode::GetOverflowFromOp:
value.GetInst()->overflow_inst = this;
break;
default:
break;
case Opcode::GetCarryFromOp:
value.GetInst()->carry_inst = this;
break;
case Opcode::GetOverflowFromOp:
value.GetInst()->overflow_inst = this;
break;
default:
break;
}
}
@@ -274,14 +274,14 @@ void Inst::UndoUse(Value& value) {
value.GetInst()->use_count--;
switch (op){
case Opcode::GetCarryFromOp:
value.GetInst()->carry_inst = nullptr;
break;
case Opcode::GetOverflowFromOp:
value.GetInst()->overflow_inst = nullptr;
break;
default:
break;
case Opcode::GetCarryFromOp:
value.GetInst()->carry_inst = nullptr;
break;
case Opcode::GetOverflowFromOp:
value.GetInst()->overflow_inst = nullptr;
break;
default:
break;
}
}

42
src/frontend/translate/translate_arm.cpp
View File

@@ -99,19 +99,19 @@ bool ArmTranslatorVisitor::LinkToNextInstruction() {
IREmitter::ResultAndCarry ArmTranslatorVisitor::EmitImmShift(IR::Value value, ShiftType type, Imm5 imm5, IR::Value carry_in) {
switch (type) {
case ShiftType::LSL:
return ir.LogicalShiftLeft(value, ir.Imm8(imm5), carry_in);
case ShiftType::LSR:
imm5 = imm5 ? imm5 : 32;
return ir.LogicalShiftRight(value, ir.Imm8(imm5), carry_in);
case ShiftType::ASR:
imm5 = imm5 ? imm5 : 32;
return ir.ArithmeticShiftRight(value, ir.Imm8(imm5), carry_in);
case ShiftType::ROR:
if (imm5)
return ir.RotateRight(value, ir.Imm8(imm5), carry_in);
else
return ir.RotateRightExtended(value, carry_in);
case ShiftType::LSL:
return ir.LogicalShiftLeft(value, ir.Imm8(imm5), carry_in);
case ShiftType::LSR:
imm5 = imm5 ? imm5 : 32;
return ir.LogicalShiftRight(value, ir.Imm8(imm5), carry_in);
case ShiftType::ASR:
imm5 = imm5 ? imm5 : 32;
return ir.ArithmeticShiftRight(value, ir.Imm8(imm5), carry_in);
case ShiftType::ROR:
if (imm5)
return ir.RotateRight(value, ir.Imm8(imm5), carry_in);
else
return ir.RotateRightExtended(value, carry_in);
}
ASSERT_MSG(false, "Unreachable");
return {};
@@ -119,14 +119,14 @@ IREmitter::ResultAndCarry ArmTranslatorVisitor::EmitImmShift(IR::Value value, Sh
IREmitter::ResultAndCarry ArmTranslatorVisitor::EmitRegShift(IR::Value value, ShiftType type, IR::Value amount, IR::Value carry_in) {
switch (type) {
case ShiftType::LSL:
return ir.LogicalShiftLeft(value, amount, carry_in);
case ShiftType::LSR:
return ir.LogicalShiftRight(value, amount, carry_in);
case ShiftType::ASR:
return ir.ArithmeticShiftRight(value, amount, carry_in);
case ShiftType::ROR:
return ir.RotateRight(value, amount, carry_in);
case ShiftType::LSL:
return ir.LogicalShiftLeft(value, amount, carry_in);
case ShiftType::LSR:
return ir.LogicalShiftRight(value, amount, carry_in);
case ShiftType::ASR:
return ir.ArithmeticShiftRight(value, amount, carry_in);
case ShiftType::ROR:
return ir.RotateRight(value, amount, carry_in);
}
ASSERT_MSG(false, "Unreachable");
return {};

22
src/frontend/translate/translate_arm/extension.cpp
View File

@@ -12,17 +12,17 @@ namespace Arm {
IR::Value ArmTranslatorVisitor::SignZeroExtendRor(Reg m, SignExtendRotation rotate) {
IR::Value rotated, reg_m = ir.GetRegister(m);
switch (rotate) {
case SignExtendRotation::ROR_0:
rotated = reg_m;
break;
case SignExtendRotation::ROR_8:
rotated = ir.RotateRight(reg_m, ir.Imm8(8), ir.Imm1(0)).result;
break;
case SignExtendRotation::ROR_16:
rotated = ir.RotateRight(reg_m, ir.Imm8(16), ir.Imm1(0)).result;
break;
case SignExtendRotation::ROR_24:
rotated = ir.RotateRight(reg_m, ir.Imm8(24), ir.Imm1(0)).result;
case SignExtendRotation::ROR_0:
rotated = reg_m;
break;
case SignExtendRotation::ROR_8:
rotated = ir.RotateRight(reg_m, ir.Imm8(8), ir.Imm1(0)).result;
break;
case SignExtendRotation::ROR_16:
rotated = ir.RotateRight(reg_m, ir.Imm8(16), ir.Imm1(0)).result;
break;
case SignExtendRotation::ROR_24:
rotated = ir.RotateRight(reg_m, ir.Imm8(24), ir.Imm1(0)).result;
}
return rotated;
}

16
src/frontend/translate/translate_arm/load_store.cpp
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@@ -217,14 +217,14 @@ bool ArmTranslatorVisitor::arm_LDRD_lit(Cond cond, bool U, Reg t, Imm4 imm8a, Im
auto data_b = ir.ReadMemory32(address_b);
switch (t) {
case Reg::PC:
data_a = ir.Add(data_a, ir.Imm32(4));
break;
case Reg::LR:
data_b = ir.Add(data_b, ir.Imm32(4));
break;
default:
break;
case Reg::PC:
data_a = ir.Add(data_a, ir.Imm32(4));
break;
case Reg::LR:
data_b = ir.Add(data_b, ir.Imm32(4));
break;
default:
break;
}
if (t == Reg::PC) {