SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-07 23:36:27 +00:00
Code Issues Packages Projects Releases Wiki Activity

TranslateArm: Implement VSTR.

Browse Source
This commit is contained in:
bunnei
2016-08-10 15:01:23 +01:00
committed by MerryMage
parent df39308e03
commit 8e8db6e137
6 changed files with 29 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/frontend/translate/translate_arm/translate_arm.h
View File

@@ -353,6 +353,7 @@ struct ArmTranslatorVisitor final {
// Floating-point load-store instructions
bool vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8);
bool vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8);
};
} // namespace Arm

18
src/frontend/translate/translate_arm/vfp2.cpp
View File

@@ -379,5 +379,23 @@ bool ArmTranslatorVisitor::vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd
return true;
}
bool ArmTranslatorVisitor::vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8) {
u32 imm32 = imm8 << 2;
ExtReg d = ToExtReg(sz, Vd, D);
// VSTR <{S,D}d>, [<Rn>, #+/-<imm32>]
if (ConditionPassed(cond)) {
auto base = n == Reg::PC ? ir.Imm32(ir.AlignPC(4)) : ir.GetRegister(n);
auto address = U ? ir.Add(base, ir.Imm32(imm32)) : ir.Sub(base, ir.Imm32(imm32));
if (sz) {
auto d_u64 = ir.TransferFromFP64(ir.GetExtendedRegister(d));
ir.WriteMemory32(address, ir.LeastSignificantWord(d_u64));
ir.WriteMemory32(ir.Add(address, ir.Imm32(4)), ir.MostSignificantWord(d_u64).result);
} else {
ir.WriteMemory32(address, ir.TransferFromFP32(ir.GetExtendedRegister(d)));
}
}
return true;
}
} // namespace Arm
} // namespace Dynarmic