SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-08 04:22:57 +00:00
Code Issues Packages Projects Releases Wiki Activity

IR: Implement FPRecipStepFused, FPVectorRecipStepFused

Browse Source
This commit is contained in:
MerryMage
2018-07-25 19:11:20 +01:00
parent f66f61d8ab
commit 901bd9b4e2
10 changed files with 135 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/frontend/ir/ir_emitter.cpp
View File

@@ -1495,6 +1495,13 @@ U32U64 IREmitter::FPRecipEstimate(const U32U64& a) {
return Inst<U64>(Opcode::FPRecipEstimate64, a);
}
U32U64 IREmitter::FPRecipStepFused(const U32U64& a, const U32U64& b) {
if (a.GetType() == Type::U32) {
return Inst<U32>(Opcode::FPRecipStepFused32, a, b);
}
return Inst<U64>(Opcode::FPRecipStepFused64, a, b);
}
U32U64 IREmitter::FPRoundInt(const U32U64& a, FP::RoundingMode rounding, bool exact) {
if (a.GetType() == Type::U32) {
return Inst<U32>(Opcode::FPRoundInt32, a, static_cast<u8>(rounding), Imm1(exact));
@@ -1760,6 +1767,17 @@ U128 IREmitter::FPVectorRecipEstimate(size_t esize, const U128& a) {
return {};
}
U128 IREmitter::FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 32:
return Inst<U128>(Opcode::FPVectorRecipStepFused32, a, b);
case 64:
return Inst<U128>(Opcode::FPVectorRecipStepFused64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorRSqrtEstimate(size_t esize, const U128& a) {
switch (esize) {
case 32: