SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-18 14:12:58 +00:00
Code Issues Packages Projects Releases Wiki Activity

A32: Implement ASIMD VRSQRTE

Browse Source
This commit is contained in:
MerryMage
2020-06-20 15:13:18 +01:00
parent 8912496206
commit 92cb4a5a34
8 changed files with 38 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
View File

@@ -379,4 +379,30 @@ bool ArmTranslatorVisitor::asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bo
return true;
}
bool ArmTranslatorVisitor::asimd_VRSQRTE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
if (sz == 0b00 || sz == 0b11) {
return UndefinedInstruction();
}
if (!F && sz == 0b01) {
// TODO: Implement 16-bit VectorUnsignedRecipEstimate
return UndefinedInstruction();
}
const size_t esize = 8U << sz;
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto reg_m = ir.GetVector(m);
const auto result = F ? ir.FPVectorRSqrtEstimate(esize, reg_m, false)
: ir.VectorUnsignedRecipSqrtEstimate(reg_m);
ir.SetVector(d, result);
return true;
}
} // namespace Dynarmic::A32