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IR: Implement FPVectorRecipEstimate

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MerryMage
2018-07-25 18:55:40 +01:00
parent 27c73dd56a
commit 939f5f5c7a
4 changed files with 31 additions and 0 deletions
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11
src/frontend/ir/ir_emitter.cpp
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@@ -1749,6 +1749,17 @@ U128 IREmitter::FPVectorPairedAddLower(size_t esize, const U128& a, const U128&
return {};
}
U128 IREmitter::FPVectorRecipEstimate(size_t esize, const U128& a) {
switch (esize) {
case 32:
return Inst<U128>(Opcode::FPVectorRecipEstimate32, a);
case 64:
return Inst<U128>(Opcode::FPVectorRecipEstimate64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorRSqrtEstimate(size_t esize, const U128& a) {
switch (esize) {
case 32:

1
src/frontend/ir/ir_emitter.h
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@@ -305,6 +305,7 @@ public:
U128 FPVectorNeg(size_t esize, const U128& a);
U128 FPVectorPairedAdd(size_t esize, const U128& a, const U128& b);
U128 FPVectorPairedAddLower(size_t esize, const U128& a, const U128& b);
U128 FPVectorRecipEstimate(size_t esize, const U128& a);
U128 FPVectorRSqrtEstimate(size_t esize, const U128& a);
U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b);
U128 FPVectorSub(size_t esize, const U128& a, const U128& b);

2
src/frontend/ir/opcodes.inc
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@@ -452,6 +452,8 @@ OPCODE(FPVectorPairedAddLower32, T::U128, T::U128,
OPCODE(FPVectorPairedAddLower64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorPairedAdd32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorPairedAdd64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorRecipEstimate32, T::U128, T::U128 )
OPCODE(FPVectorRecipEstimate64, T::U128, T::U128 )
OPCODE(FPVectorRSqrtEstimate32, T::U128, T::U128 )
OPCODE(FPVectorRSqrtEstimate64, T::U128, T::U128 )
OPCODE(FPVectorRSqrtStepFused32, T::U128, T::U128, T::U128 )