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A32: Implement ASIMD VCLS/VCLZ/VCNT

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This commit is contained in:
Lioncash
2020-06-15 22:17:33 -04:00
committed by merry
parent 9b06a938a9
commit 93ed3441b7
3 changed files with 81 additions and 3 deletions
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75
src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
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@@ -9,6 +9,81 @@
namespace Dynarmic::A32 {
bool ArmTranslatorVisitor::asimd_VCLS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) {
if (sz == 0b11) {
return UndefinedInstruction();
}
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto result = [this, m, sz] {
const auto reg_m = ir.GetVector(m);
const size_t esize = 8U << sz;
const auto one = [this, esize]() -> IR::UAny {
switch (esize) {
case 8:
return ir.Imm8(1);
case 16:
return ir.Imm16(1);
default:
return ir.Imm32(1);
}
}();
const auto shifted = ir.VectorArithmeticShiftRight(esize, reg_m, static_cast<u8>(esize));
const auto xored = ir.VectorEor(reg_m, shifted);
const auto clz = ir.VectorCountLeadingZeros(esize, xored);
return ir.VectorSub(esize, clz, ir.VectorBroadcast(esize, one));
}();
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VCLZ(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) {
if (sz == 0b11) {
return UndefinedInstruction();
}
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto result = [this, m, sz] {
const auto reg_m = ir.GetVector(m);
const size_t esize = 8U << sz;
return ir.VectorCountLeadingZeros(esize, reg_m);
}();
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VCNT(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) {
if (sz != 0b00) {
return UndefinedInstruction();
}
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto reg_m = ir.GetVector(m);
const auto result = ir.VectorPopulationCount(reg_m);
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) {
if (sz == 0b11 || (F && sz != 0b10)) {
return UndefinedInstruction();