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Optimization: Implement Return Stack Buffer

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This commit is contained in:
MerryMage
2016-08-13 00:10:23 +01:00
parent 8e68e6fdd9
commit 960d14d18e
18 changed files with 167 additions and 31 deletions
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21
src/frontend/arm_types.h
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@@ -71,10 +71,10 @@ enum class SignExtendRotation {
* tells us if the processor is in Thumb or Arm mode.
*/
struct LocationDescriptor {
static constexpr u32 FPSCR_MASK = 0x3F79F9F;
static constexpr u32 FPSCR_MODE_MASK = 0x03F79F00;
LocationDescriptor(u32 arm_pc, bool tflag, bool eflag, u32 fpscr)
: arm_pc(arm_pc), tflag(tflag), eflag(eflag), fpscr(fpscr & FPSCR_MASK) {}
: arm_pc(arm_pc), tflag(tflag), eflag(eflag), fpscr(fpscr & FPSCR_MODE_MASK) {}
u32 PC() const { return arm_pc; }
bool TFlag() const { return tflag; }
@@ -106,7 +106,17 @@ struct LocationDescriptor {
}
LocationDescriptor SetFPSCR(u32 new_fpscr) const {
return LocationDescriptor(arm_pc, tflag, eflag, new_fpscr & FPSCR_MASK);
return LocationDescriptor(arm_pc, tflag, eflag, new_fpscr & FPSCR_MODE_MASK);
}
u64 UniqueHash() const {
// This value MUST BE UNIQUE.
// This calculation has to match up with EmitX64::EmitTerminalPopRSBHint
u64 pc_u64 = u64(arm_pc);
u64 fpscr_u64 = u64(fpscr) << 32;
u64 t_u64 = tflag ? (1ull << 35) : 0;
u64 e_u64 = eflag ? (1ull << 39) : 0;
return pc_u64 | fpscr_u64 | t_u64 | e_u64;
}
private:
@@ -118,10 +128,7 @@ private:
struct LocationDescriptorHash {
size_t operator()(const LocationDescriptor& x) const {
return std::hash<u64>()(static_cast<u64>(x.PC())
^ static_cast<u64>(x.TFlag())
^ (static_cast<u64>(x.EFlag()) << 1)
^ (static_cast<u64>(x.FPSCR()) << 32));
return std::hash<u64>()(x.UniqueHash());
}
};

11
src/frontend/ir/ir.cpp
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@@ -41,6 +41,10 @@ Value::Value(u32 value) : type(Type::U32) {
inner.imm_u32 = value;
}
Value::Value(u64 value) : type(Type::U64) {
inner.imm_u64 = value;
}
bool Value::IsImmediate() const {
if (type == Type::Opaque)
return inner.inst->GetOpcode() == Opcode::Identity ? inner.inst->GetArg(0).IsImmediate() : false;
@@ -98,6 +102,13 @@ u32 Value::GetU32() const {
return inner.imm_u32;
}
u64 Value::GetU64() const {
if (type == Type::Opaque && inner.inst->GetOpcode() == Opcode::Identity)
return inner.inst->GetArg(0).GetU64();
DEBUG_ASSERT(type == Type::U64);
return inner.imm_u64;
}
// Inst class member definitions
Value Inst::GetArg(size_t index) const {

3
src/frontend/ir/ir.h
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@@ -50,6 +50,7 @@ public:
explicit Value(bool value);
explicit Value(u8 value);
explicit Value(u32 value);
explicit Value(u64 value);
bool IsEmpty() const;
bool IsImmediate() const;
@@ -61,6 +62,7 @@ public:
bool GetU1() const;
u8 GetU8() const;
u32 GetU32() const;
u64 GetU64() const;
private:
Type type;
@@ -72,6 +74,7 @@ private:
bool imm_u1;
u8 imm_u8;
u32 imm_u32;
u64 imm_u64;
} inner;
};

4
src/frontend/ir/ir_emitter.cpp
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@@ -98,6 +98,10 @@ void IREmitter::CallSupervisor(const IR::Value& value) {
Inst(IR::Opcode::CallSupervisor, {value});
}
void IREmitter::PushRSB(const LocationDescriptor& return_location) {
Inst(IR::Opcode::PushRSB, {IR::Value(return_location.UniqueHash())});
}
IR::Value IREmitter::GetCFlag() {
return Inst(IR::Opcode::GetCFlag, {});
}

1
src/frontend/ir/ir_emitter.h
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@@ -54,6 +54,7 @@ public:
void BXWritePC(const IR::Value& value);
void LoadWritePC(const IR::Value& value);
void CallSupervisor(const IR::Value& value);
void PushRSB(const LocationDescriptor& return_location);
IR::Value GetCFlag();
void SetNFlag(const IR::Value& value);

3
src/frontend/ir/opcodes.inc
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@@ -22,6 +22,9 @@ OPCODE(OrQFlag, T::Void, T::U1
OPCODE(BXWritePC, T::Void, T::U32 )
OPCODE(CallSupervisor, T::Void, T::U32 )
// Hints
OPCODE(PushRSB, T::Void, T::U64 )
// Pseudo-operation, handled specially at final emit
OPCODE(GetCarryFromOp, T::U1, T::U32 )
OPCODE(GetOverflowFromOp, T::U1, T::U32 )

8
src/frontend/translate/translate_arm/branch.cpp
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@@ -26,6 +26,7 @@ bool ArmTranslatorVisitor::arm_BL(Cond cond, Imm24 imm24) {
u32 imm32 = Common::SignExtend<26, u32>(imm24 << 2) + 8;
// BL <label>
if (ConditionPassed(cond)) {
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.SetRegister(Reg::LR, ir.Imm32(ir.current_location.PC() + 4));
auto new_location = ir.current_location.AdvancePC(imm32);
ir.SetTerm(IR::Term::LinkBlock{ new_location });
@@ -37,6 +38,7 @@ bool ArmTranslatorVisitor::arm_BL(Cond cond, Imm24 imm24) {
bool ArmTranslatorVisitor::arm_BLX_imm(bool H, Imm24 imm24) {
u32 imm32 = Common::SignExtend<26, u32>((imm24 << 2)) + (H ? 2 : 0) + 8;
// BLX <label>
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.SetRegister(Reg::LR, ir.Imm32(ir.current_location.PC() + 4));
auto new_location = ir.current_location.AdvancePC(imm32).SetTFlag(true);
ir.SetTerm(IR::Term::LinkBlock{ new_location });
@@ -48,6 +50,7 @@ bool ArmTranslatorVisitor::arm_BLX_reg(Cond cond, Reg m) {
return UnpredictableInstruction();
// BLX <Rm>
if (ConditionPassed(cond)) {
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.SetRegister(Reg::LR, ir.Imm32(ir.current_location.PC() + 4));
ir.BXWritePC(ir.GetRegister(m));
ir.SetTerm(IR::Term::ReturnToDispatch{});
@@ -60,7 +63,10 @@ bool ArmTranslatorVisitor::arm_BX(Cond cond, Reg m) {
// BX <Rm>
if (ConditionPassed(cond)) {
ir.BXWritePC(ir.GetRegister(m));
ir.SetTerm(IR::Term::ReturnToDispatch{});
if (m == Reg::R14)
ir.SetTerm(IR::Term::PopRSBHint{});
else
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
return true;

10
src/frontend/translate/translate_arm/load_store.cpp
View File

@@ -44,7 +44,10 @@ bool ArmTranslatorVisitor::arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n,
if (d == Reg::PC) {
ir.BXWritePC(data);
ir.SetTerm(IR::Term::ReturnToDispatch{});
if (!P && W && n == Reg::R13)
ir.SetTerm(IR::Term::PopRSBHint{});
else
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
@@ -413,7 +416,10 @@ static bool LDMHelper(IREmitter& ir, bool W, Reg n, RegList list, IR::Value star
}
if (Common::Bit<15>(list)) {
ir.LoadWritePC(ir.ReadMemory32(address));
ir.SetTerm(IR::Term::ReturnToDispatch{});
if (n == Reg::R13)
ir.SetTerm(IR::Term::PopRSBHint{});
else
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
return true;

9
src/frontend/translate/translate_thumb.cpp
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@@ -753,15 +753,18 @@ struct ThumbTranslatorVisitor final {
bool thumb16_BX(Reg m) {
// BX <Rm>
ir.BXWritePC(ir.GetRegister(m));
ir.SetTerm(IR::Term::ReturnToDispatch{});
if (m == Reg::R14)
ir.SetTerm(IR::Term::PopRSBHint{});
else
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
bool thumb16_BLX_reg(Reg m) {
// BLX <Rm>
ir.PushRSB(ir.current_location.AdvancePC(2));
ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 2) | 1));
ir.BXWritePC(ir.GetRegister(m));
// TODO(optimization): Possible push RSB location
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
@@ -798,6 +801,7 @@ struct ThumbTranslatorVisitor final {
bool thumb32_BL_imm(Imm11 hi, Imm11 lo) {
s32 imm32 = Common::SignExtend<23, s32>((hi << 12) | (lo << 1)) + 4;
// BL <label>
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 4) | 1));
auto new_location = ir.current_location.AdvancePC(imm32);
ir.SetTerm(IR::Term::LinkBlock{new_location});
@@ -810,6 +814,7 @@ struct ThumbTranslatorVisitor final {
return UnpredictableInstruction();
}
// BLX <label>
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 4) | 1));
auto new_location = ir.current_location
.SetPC(ir.AlignPC(4) + imm32)