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Optimization: Implement Return Stack Buffer

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This commit is contained in:
MerryMage
2016-08-13 00:10:23 +01:00
parent 8e68e6fdd9
commit 960d14d18e
18 changed files with 167 additions and 31 deletions
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8
src/frontend/translate/translate_arm/branch.cpp
View File

@@ -26,6 +26,7 @@ bool ArmTranslatorVisitor::arm_BL(Cond cond, Imm24 imm24) {
u32 imm32 = Common::SignExtend<26, u32>(imm24 << 2) + 8;
// BL <label>
if (ConditionPassed(cond)) {
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.SetRegister(Reg::LR, ir.Imm32(ir.current_location.PC() + 4));
auto new_location = ir.current_location.AdvancePC(imm32);
ir.SetTerm(IR::Term::LinkBlock{ new_location });
@@ -37,6 +38,7 @@ bool ArmTranslatorVisitor::arm_BL(Cond cond, Imm24 imm24) {
bool ArmTranslatorVisitor::arm_BLX_imm(bool H, Imm24 imm24) {
u32 imm32 = Common::SignExtend<26, u32>((imm24 << 2)) + (H ? 2 : 0) + 8;
// BLX <label>
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.SetRegister(Reg::LR, ir.Imm32(ir.current_location.PC() + 4));
auto new_location = ir.current_location.AdvancePC(imm32).SetTFlag(true);
ir.SetTerm(IR::Term::LinkBlock{ new_location });
@@ -48,6 +50,7 @@ bool ArmTranslatorVisitor::arm_BLX_reg(Cond cond, Reg m) {
return UnpredictableInstruction();
// BLX <Rm>
if (ConditionPassed(cond)) {
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.SetRegister(Reg::LR, ir.Imm32(ir.current_location.PC() + 4));
ir.BXWritePC(ir.GetRegister(m));
ir.SetTerm(IR::Term::ReturnToDispatch{});
@@ -60,7 +63,10 @@ bool ArmTranslatorVisitor::arm_BX(Cond cond, Reg m) {
// BX <Rm>
if (ConditionPassed(cond)) {
ir.BXWritePC(ir.GetRegister(m));
ir.SetTerm(IR::Term::ReturnToDispatch{});
if (m == Reg::R14)
ir.SetTerm(IR::Term::PopRSBHint{});
else
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
return true;

10
src/frontend/translate/translate_arm/load_store.cpp
View File

@@ -44,7 +44,10 @@ bool ArmTranslatorVisitor::arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n,
if (d == Reg::PC) {
ir.BXWritePC(data);
ir.SetTerm(IR::Term::ReturnToDispatch{});
if (!P && W && n == Reg::R13)
ir.SetTerm(IR::Term::PopRSBHint{});
else
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
@@ -413,7 +416,10 @@ static bool LDMHelper(IREmitter& ir, bool W, Reg n, RegList list, IR::Value star
}
if (Common::Bit<15>(list)) {
ir.LoadWritePC(ir.ReadMemory32(address));
ir.SetTerm(IR::Term::ReturnToDispatch{});
if (n == Reg::R13)
ir.SetTerm(IR::Term::PopRSBHint{});
else
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
return true;

9
src/frontend/translate/translate_thumb.cpp
View File

@@ -753,15 +753,18 @@ struct ThumbTranslatorVisitor final {
bool thumb16_BX(Reg m) {
// BX <Rm>
ir.BXWritePC(ir.GetRegister(m));
ir.SetTerm(IR::Term::ReturnToDispatch{});
if (m == Reg::R14)
ir.SetTerm(IR::Term::PopRSBHint{});
else
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
bool thumb16_BLX_reg(Reg m) {
// BLX <Rm>
ir.PushRSB(ir.current_location.AdvancePC(2));
ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 2) | 1));
ir.BXWritePC(ir.GetRegister(m));
// TODO(optimization): Possible push RSB location
ir.SetTerm(IR::Term::ReturnToDispatch{});
return false;
}
@@ -798,6 +801,7 @@ struct ThumbTranslatorVisitor final {
bool thumb32_BL_imm(Imm11 hi, Imm11 lo) {
s32 imm32 = Common::SignExtend<23, s32>((hi << 12) | (lo << 1)) + 4;
// BL <label>
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 4) | 1));
auto new_location = ir.current_location.AdvancePC(imm32);
ir.SetTerm(IR::Term::LinkBlock{new_location});
@@ -810,6 +814,7 @@ struct ThumbTranslatorVisitor final {
return UnpredictableInstruction();
}
// BLX <label>
ir.PushRSB(ir.current_location.AdvancePC(4));
ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 4) | 1));
auto new_location = ir.current_location
.SetPC(ir.AlignPC(4) + imm32)