mirror of
https://git.suyu.dev/suyu/dynarmic.git
synced 2026-03-10 17:16:27 +00:00
Exclusive Monitor: Rework exclusive monitor interface.
This commit is contained in:
committed by
MerryMage
parent
b5d8b24a3c
commit
97b9d3e058
@@ -100,11 +100,6 @@ void IREmitter::ClearExclusive() {
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Inst(Opcode::A64ClearExclusive);
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}
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void IREmitter::SetExclusive(const IR::U64& vaddr, size_t byte_size) {
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ASSERT(byte_size == 1 || byte_size == 2 || byte_size == 4 || byte_size == 8 || byte_size == 16);
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Inst(Opcode::A64SetExclusive, vaddr, Imm8(u8(byte_size)));
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}
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IR::U8 IREmitter::ReadMemory8(const IR::U64& vaddr) {
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return Inst<IR::U8>(Opcode::A64ReadMemory8, vaddr);
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}
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@@ -125,6 +120,26 @@ IR::U128 IREmitter::ReadMemory128(const IR::U64& vaddr) {
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return Inst<IR::U128>(Opcode::A64ReadMemory128, vaddr);
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}
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IR::U8 IREmitter::ExclusiveReadMemory8(const IR::U64& vaddr) {
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return Inst<IR::U8>(Opcode::A64ExclusiveReadMemory8, vaddr);
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}
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IR::U16 IREmitter::ExclusiveReadMemory16(const IR::U64& vaddr) {
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return Inst<IR::U16>(Opcode::A64ExclusiveReadMemory16, vaddr);
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}
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IR::U32 IREmitter::ExclusiveReadMemory32(const IR::U64& vaddr) {
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return Inst<IR::U32>(Opcode::A64ExclusiveReadMemory32, vaddr);
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}
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IR::U64 IREmitter::ExclusiveReadMemory64(const IR::U64& vaddr) {
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return Inst<IR::U64>(Opcode::A64ExclusiveReadMemory64, vaddr);
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}
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IR::U128 IREmitter::ExclusiveReadMemory128(const IR::U64& vaddr) {
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return Inst<IR::U128>(Opcode::A64ExclusiveReadMemory128, vaddr);
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}
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void IREmitter::WriteMemory8(const IR::U64& vaddr, const IR::U8& value) {
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Inst(Opcode::A64WriteMemory8, vaddr, value);
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}
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@@ -54,12 +54,16 @@ public:
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void SetTPIDR(const IR::U64& value);
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void ClearExclusive();
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void SetExclusive(const IR::U64& vaddr, size_t byte_size);
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IR::U8 ReadMemory8(const IR::U64& vaddr);
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IR::U16 ReadMemory16(const IR::U64& vaddr);
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IR::U32 ReadMemory32(const IR::U64& vaddr);
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IR::U64 ReadMemory64(const IR::U64& vaddr);
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IR::U128 ReadMemory128(const IR::U64& vaddr);
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IR::U8 ExclusiveReadMemory8(const IR::U64& vaddr);
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IR::U16 ExclusiveReadMemory16(const IR::U64& vaddr);
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IR::U32 ExclusiveReadMemory32(const IR::U64& vaddr);
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IR::U64 ExclusiveReadMemory64(const IR::U64& vaddr);
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IR::U128 ExclusiveReadMemory128(const IR::U64& vaddr);
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void WriteMemory8(const IR::U64& vaddr, const IR::U8& value);
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void WriteMemory16(const IR::U64& vaddr, const IR::U16& value);
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void WriteMemory32(const IR::U64& vaddr, const IR::U32& value);
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@@ -308,7 +308,24 @@ void TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, IR::AccType /*acc_
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}
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}
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IR::U32 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, IR::AccType /*acc_type*/, IR::UAnyU128 value) {
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IR::UAnyU128 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, IR::AccType /*acctype*/) {
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switch (bytesize) {
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case 1:
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return ir.ExclusiveReadMemory8(address);
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case 2:
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return ir.ExclusiveReadMemory16(address);
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case 4:
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return ir.ExclusiveReadMemory32(address);
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case 8:
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return ir.ExclusiveReadMemory64(address);
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case 16:
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return ir.ExclusiveReadMemory128(address);
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default:
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ASSERT_FALSE("Invalid bytesize parameter {}", bytesize);
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}
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}
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IR::U32 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, IR::AccType /*acctype*/, IR::UAnyU128 value) {
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switch (bytesize) {
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case 1:
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return ir.ExclusiveWriteMemory8(address, value);
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@@ -57,6 +57,7 @@ struct TranslatorVisitor final {
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IR::UAnyU128 Mem(IR::U64 address, size_t size, IR::AccType acctype);
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void Mem(IR::U64 address, size_t size, IR::AccType acctype, IR::UAnyU128 value);
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IR::UAnyU128 ExclusiveMem(IR::U64 address, size_t size, IR::AccType acctype);
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IR::U32 ExclusiveMem(IR::U64 address, size_t size, IR::AccType acctype, IR::UAnyU128 value);
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IR::U32U64 SignExtend(IR::UAny value, size_t to_size);
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@@ -56,8 +56,7 @@ static bool ExclusiveSharedDecodeAndOperation(TranslatorVisitor& v, bool pair, s
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break;
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}
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case IR::MemOp::LOAD: {
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v.ir.SetExclusive(address, dbytes);
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const IR::UAnyU128 data = v.Mem(address, dbytes, acctype);
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const IR::UAnyU128 data = v.ExclusiveMem(address, dbytes, acctype);
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if (pair && elsize == 64) {
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v.X(64, Rt, v.ir.VectorGetElement(64, data, 0));
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v.X(64, *Rt2, v.ir.VectorGetElement(64, data, 1));
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@@ -99,6 +99,20 @@ bool Inst::IsSharedMemoryReadOrWrite() const {
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return IsSharedMemoryRead() || IsSharedMemoryWrite();
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}
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bool Inst::IsExclusiveMemoryRead() const {
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switch (op) {
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case Opcode::A64ExclusiveReadMemory8:
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case Opcode::A64ExclusiveReadMemory16:
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case Opcode::A64ExclusiveReadMemory32:
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case Opcode::A64ExclusiveReadMemory64:
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case Opcode::A64ExclusiveReadMemory128:
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return true;
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default:
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return false;
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}
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}
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bool Inst::IsExclusiveMemoryWrite() const {
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switch (op) {
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case Opcode::A32ExclusiveWriteMemory8:
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@@ -118,7 +132,7 @@ bool Inst::IsExclusiveMemoryWrite() const {
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}
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bool Inst::IsMemoryRead() const {
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return IsSharedMemoryRead();
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return IsSharedMemoryRead() || IsExclusiveMemoryRead();
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}
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bool Inst::IsMemoryWrite() const {
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@@ -457,7 +471,7 @@ bool Inst::AltersExclusiveState() const {
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return op == Opcode::A32ClearExclusive ||
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op == Opcode::A32SetExclusive ||
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op == Opcode::A64ClearExclusive ||
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op == Opcode::A64SetExclusive ||
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IsExclusiveMemoryRead() ||
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IsExclusiveMemoryWrite();
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}
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@@ -44,6 +44,8 @@ public:
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bool IsSharedMemoryWrite() const;
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/// Determines whether or not this instruction performs a shared memory read or write.
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bool IsSharedMemoryReadOrWrite() const;
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/// Determines whether or not this instruction performs an atomic memory read.
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bool IsExclusiveMemoryRead() const;
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/// Determines whether or not this instruction performs an atomic memory write.
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bool IsExclusiveMemoryWrite() const;
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@@ -637,12 +637,16 @@ A32OPC(ExclusiveWriteMemory64, U32, U32,
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// A64 Memory access
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A64OPC(ClearExclusive, Void, )
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A64OPC(SetExclusive, Void, U64, U8 )
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A64OPC(ReadMemory8, U8, U64 )
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A64OPC(ReadMemory16, U16, U64 )
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A64OPC(ReadMemory32, U32, U64 )
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A64OPC(ReadMemory64, U64, U64 )
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A64OPC(ReadMemory128, U128, U64 )
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A64OPC(ExclusiveReadMemory8, U8, U64 )
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A64OPC(ExclusiveReadMemory16, U16, U64 )
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A64OPC(ExclusiveReadMemory32, U32, U64 )
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A64OPC(ExclusiveReadMemory64, U64, U64 )
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A64OPC(ExclusiveReadMemory128, U128, U64 )
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A64OPC(WriteMemory8, Void, U64, U8 )
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A64OPC(WriteMemory16, Void, U64, U16 )
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A64OPC(WriteMemory32, Void, U64, U32 )
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