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A64: Implement FCMEQ (register)'s vector single and double precision variant

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This commit is contained in:
Lioncash
2018-06-02 16:17:15 -04:00
committed by MerryMage
parent 5ce187a54e
commit 9bec354791
2 changed files with 17 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@@ -729,7 +729,7 @@ INST(ADDP_vec, "ADDP (vector)", "0Q001
INST(FADD_2, "FADD (vector)", "0Q0011100z1mmmmm110101nnnnnddddd")
//INST(FMAX_2, "FMAX (vector)", "0Q0011100z1mmmmm111101nnnnnddddd")
//INST(FMULX_vec_4, "FMULX", "0Q0011100z1mmmmm110111nnnnnddddd")
//INST(FCMEQ_reg_4, "FCMEQ (register)", "0Q0011100z1mmmmm111001nnnnnddddd")
INST(FCMEQ_reg_4, "FCMEQ (register)", "0Q0011100z1mmmmm111001nnnnnddddd")
//INST(FMLAL_vec_1, "FMLAL, FMLAL2 (vector)", "0Q0011100z1mmmmm111011nnnnnddddd")
//INST(FRECPS_4, "FRECPS", "0Q0011100z1mmmmm111111nnnnnddddd")
INST(AND_asimd, "AND (vector)", "0Q001110001mmmmm000111nnnnnddddd")