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A64: Implement SADDLP

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This commit is contained in:
MerryMage
2018-07-15 18:48:11 +01:00
parent 70ff2d73b5
commit 9dba273a8c
6 changed files with 91 additions and 8 deletions
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2
src/frontend/A64/decoder/a64.inc
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@@ -568,7 +568,7 @@ INST(INS_elt, "INS (element)", "01101
// Data Processing - FP and SIMD - SIMD Two-register misc
INST(REV64_asimd, "REV64", "0Q001110zz100000000010nnnnnddddd")
INST(REV16_asimd, "REV16 (vector)", "0Q001110zz100000000110nnnnnddddd")
//INST(SADDLP, "SADDLP", "0Q001110zz100000001010nnnnnddddd")
INST(SADDLP, "SADDLP", "0Q001110zz100000001010nnnnnddddd")
//INST(SUQADD_2, "SUQADD", "0Q001110zz100000001110nnnnnddddd")
//INST(CLS_asimd, "CLS (vector)", "0Q001110zz100000010010nnnnnddddd")
INST(CNT, "CNT", "0Q001110zz100000010110nnnnnddddd")

19
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
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@@ -384,6 +384,25 @@ bool TranslatorVisitor::UADDLP(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::SADDLP(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend();
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand = V(datasize, Vn);
IR::U128 result = ir.VectorPairedAddSignedWiden(esize, operand);
if (datasize == 64) {
result = ir.VectorZeroUpper(result);
}
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::SCVTF_int_4(bool Q, bool sz, Vec Vn, Vec Vd) {
return IntegerConvertToFloat(*this, Q, sz, Vn, Vd, Signedness::Signed);
}