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https://git.suyu.dev/suyu/dynarmic.git
synced 2026-02-18 22:42:58 +00:00
IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
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@@ -154,7 +154,7 @@ IR::U32 IREmitter::GetFpscrNZCV() {
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return Inst<IR::U32>(Opcode::A32GetFpscrNZCV);
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}
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void IREmitter::SetFpscrNZCV(const IR::U32& new_fpscr_nzcv) {
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void IREmitter::SetFpscrNZCV(const IR::NZCV& new_fpscr_nzcv) {
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Inst(Opcode::A32SetFpscrNZCV, new_fpscr_nzcv);
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}
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@@ -64,7 +64,7 @@ public:
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IR::U32 GetFpscr();
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void SetFpscr(const IR::U32& new_fpscr);
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IR::U32 GetFpscrNZCV();
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void SetFpscrNZCV(const IR::U32& new_fpscr_nzcv);
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void SetFpscrNZCV(const IR::NZCV& new_fpscr_nzcv);
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void ClearExclusive();
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void SetExclusive(const IR::U32& vaddr, size_t byte_size);
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@@ -473,7 +473,8 @@ bool ArmTranslatorVisitor::vfp2_VCMP(Cond cond, bool D, size_t Vd, bool sz, bool
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if (ConditionPassed(cond)) {
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auto reg_d = ir.GetExtendedRegister(d);
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auto reg_m = ir.GetExtendedRegister(m);
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ir.FPCompare(reg_d, reg_m, exc_on_qnan, true);
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auto nzcv = ir.FPCompare(reg_d, reg_m, exc_on_qnan, true);
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ir.SetFpscrNZCV(nzcv);
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}
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return true;
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}
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@@ -486,9 +487,11 @@ bool ArmTranslatorVisitor::vfp2_VCMP_zero(Cond cond, bool D, size_t Vd, bool sz,
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if (ConditionPassed(cond)) {
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auto reg_d = ir.GetExtendedRegister(d);
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if (sz) {
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ir.FPCompare(reg_d, ir.Imm64(0), exc_on_qnan, true);
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auto nzcv = ir.FPCompare(reg_d, ir.Imm64(0), exc_on_qnan, true);
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ir.SetFpscrNZCV(nzcv);
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} else {
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ir.FPCompare(reg_d, ir.Imm32(0), exc_on_qnan, true);
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auto nzcv = ir.FPCompare(reg_d, ir.Imm32(0), exc_on_qnan, true);
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ir.SetFpscrNZCV(nzcv);
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}
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}
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return true;
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@@ -37,7 +37,8 @@ bool TranslatorVisitor::FCMP_float(Imm<2> type, Vec Vm, Vec Vn, bool cmp_with_ze
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operand2 = V_scalar(*datasize, Vm);
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}
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ir.FPCompare(operand1, operand2, false, true);
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auto nzcv = ir.FPCompare(operand1, operand2, false, true);
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ir.SetNZCV(nzcv);
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return true;
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}
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@@ -55,7 +56,8 @@ bool TranslatorVisitor::FCMPE_float(Imm<2> type, Vec Vm, Vec Vn, bool cmp_with_z
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operand2 = V_scalar(*datasize, Vm);
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}
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ir.FPCompare(operand1, operand2, true, true);
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auto nzcv = ir.FPCompare(operand1, operand2, true, true);
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ir.SetNZCV(nzcv);
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return true;
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}
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@@ -907,13 +907,13 @@ U32U64 IREmitter::FPAdd(const U32U64& a, const U32U64& b, bool fpscr_controlled)
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}
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}
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void IREmitter::FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan, bool fpscr_controlled) {
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NZCV IREmitter::FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan, bool fpscr_controlled) {
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ASSERT(fpscr_controlled);
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ASSERT(a.GetType() == b.GetType());
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if (a.GetType() == Type::U32) {
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Inst(Opcode::FPCompare32, a, b, Imm1(exc_on_qnan));
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return Inst<NZCV>(Opcode::FPCompare32, a, b, Imm1(exc_on_qnan));
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} else {
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Inst(Opcode::FPCompare64, a, b, Imm1(exc_on_qnan));
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return Inst<NZCV>(Opcode::FPCompare64, a, b, Imm1(exc_on_qnan));
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}
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}
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@@ -236,7 +236,7 @@ public:
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U32U64 FPAbs(const U32U64& a);
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U32U64 FPAdd(const U32U64& a, const U32U64& b, bool fpscr_controlled);
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void FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan, bool fpscr_controlled);
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NZCV FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan, bool fpscr_controlled);
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U32U64 FPDiv(const U32U64& a, const U32U64& b, bool fpscr_controlled);
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U32U64 FPMul(const U32U64& a, const U32U64& b, bool fpscr_controlled);
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U32U64 FPNeg(const U32U64& a);
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@@ -33,7 +33,7 @@ A32OPC(ExceptionRaised, T::Void, T::U32, T::U64
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A32OPC(GetFpscr, T::U32, )
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A32OPC(SetFpscr, T::Void, T::U32, )
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A32OPC(GetFpscrNZCV, T::U32, )
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A32OPC(SetFpscrNZCV, T::Void, T::U32, )
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A32OPC(SetFpscrNZCV, T::Void, T::NZCVFlags )
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// A64 Context getters/setters
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A64OPC(SetCheckBit, T::Void, T::U1 )
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@@ -230,8 +230,8 @@ OPCODE(FPAbs32, T::U32, T::U32
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OPCODE(FPAbs64, T::U64, T::U64 )
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OPCODE(FPAdd32, T::U32, T::U32, T::U32 )
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OPCODE(FPAdd64, T::U64, T::U64, T::U64 )
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OPCODE(FPCompare32, T::Void, T::U32, T::U32, T::U1 )
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OPCODE(FPCompare64, T::Void, T::U64, T::U64, T::U1 )
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OPCODE(FPCompare32, T::NZCVFlags, T::U32, T::U32, T::U1 )
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OPCODE(FPCompare64, T::NZCVFlags, T::U64, T::U64, T::U1 )
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OPCODE(FPDiv32, T::U32, T::U32, T::U32 )
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OPCODE(FPDiv64, T::U64, T::U64, T::U64 )
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OPCODE(FPMul32, T::U32, T::U32, T::U32 )
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