IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them

This commit is contained in:
MerryMage
2018-02-05 12:16:01 +00:00
parent 2ee39d6b36
commit aac5af50e2
10 changed files with 51 additions and 26 deletions

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@@ -154,7 +154,7 @@ IR::U32 IREmitter::GetFpscrNZCV() {
return Inst<IR::U32>(Opcode::A32GetFpscrNZCV);
}
void IREmitter::SetFpscrNZCV(const IR::U32& new_fpscr_nzcv) {
void IREmitter::SetFpscrNZCV(const IR::NZCV& new_fpscr_nzcv) {
Inst(Opcode::A32SetFpscrNZCV, new_fpscr_nzcv);
}

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@@ -64,7 +64,7 @@ public:
IR::U32 GetFpscr();
void SetFpscr(const IR::U32& new_fpscr);
IR::U32 GetFpscrNZCV();
void SetFpscrNZCV(const IR::U32& new_fpscr_nzcv);
void SetFpscrNZCV(const IR::NZCV& new_fpscr_nzcv);
void ClearExclusive();
void SetExclusive(const IR::U32& vaddr, size_t byte_size);

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@@ -473,7 +473,8 @@ bool ArmTranslatorVisitor::vfp2_VCMP(Cond cond, bool D, size_t Vd, bool sz, bool
if (ConditionPassed(cond)) {
auto reg_d = ir.GetExtendedRegister(d);
auto reg_m = ir.GetExtendedRegister(m);
ir.FPCompare(reg_d, reg_m, exc_on_qnan, true);
auto nzcv = ir.FPCompare(reg_d, reg_m, exc_on_qnan, true);
ir.SetFpscrNZCV(nzcv);
}
return true;
}
@@ -486,9 +487,11 @@ bool ArmTranslatorVisitor::vfp2_VCMP_zero(Cond cond, bool D, size_t Vd, bool sz,
if (ConditionPassed(cond)) {
auto reg_d = ir.GetExtendedRegister(d);
if (sz) {
ir.FPCompare(reg_d, ir.Imm64(0), exc_on_qnan, true);
auto nzcv = ir.FPCompare(reg_d, ir.Imm64(0), exc_on_qnan, true);
ir.SetFpscrNZCV(nzcv);
} else {
ir.FPCompare(reg_d, ir.Imm32(0), exc_on_qnan, true);
auto nzcv = ir.FPCompare(reg_d, ir.Imm32(0), exc_on_qnan, true);
ir.SetFpscrNZCV(nzcv);
}
}
return true;

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@@ -37,7 +37,8 @@ bool TranslatorVisitor::FCMP_float(Imm<2> type, Vec Vm, Vec Vn, bool cmp_with_ze
operand2 = V_scalar(*datasize, Vm);
}
ir.FPCompare(operand1, operand2, false, true);
auto nzcv = ir.FPCompare(operand1, operand2, false, true);
ir.SetNZCV(nzcv);
return true;
}
@@ -55,7 +56,8 @@ bool TranslatorVisitor::FCMPE_float(Imm<2> type, Vec Vm, Vec Vn, bool cmp_with_z
operand2 = V_scalar(*datasize, Vm);
}
ir.FPCompare(operand1, operand2, true, true);
auto nzcv = ir.FPCompare(operand1, operand2, true, true);
ir.SetNZCV(nzcv);
return true;
}

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@@ -907,13 +907,13 @@ U32U64 IREmitter::FPAdd(const U32U64& a, const U32U64& b, bool fpscr_controlled)
}
}
void IREmitter::FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan, bool fpscr_controlled) {
NZCV IREmitter::FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan, bool fpscr_controlled) {
ASSERT(fpscr_controlled);
ASSERT(a.GetType() == b.GetType());
if (a.GetType() == Type::U32) {
Inst(Opcode::FPCompare32, a, b, Imm1(exc_on_qnan));
return Inst<NZCV>(Opcode::FPCompare32, a, b, Imm1(exc_on_qnan));
} else {
Inst(Opcode::FPCompare64, a, b, Imm1(exc_on_qnan));
return Inst<NZCV>(Opcode::FPCompare64, a, b, Imm1(exc_on_qnan));
}
}

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@@ -236,7 +236,7 @@ public:
U32U64 FPAbs(const U32U64& a);
U32U64 FPAdd(const U32U64& a, const U32U64& b, bool fpscr_controlled);
void FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan, bool fpscr_controlled);
NZCV FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan, bool fpscr_controlled);
U32U64 FPDiv(const U32U64& a, const U32U64& b, bool fpscr_controlled);
U32U64 FPMul(const U32U64& a, const U32U64& b, bool fpscr_controlled);
U32U64 FPNeg(const U32U64& a);

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@@ -33,7 +33,7 @@ A32OPC(ExceptionRaised, T::Void, T::U32, T::U64
A32OPC(GetFpscr, T::U32, )
A32OPC(SetFpscr, T::Void, T::U32, )
A32OPC(GetFpscrNZCV, T::U32, )
A32OPC(SetFpscrNZCV, T::Void, T::U32, )
A32OPC(SetFpscrNZCV, T::Void, T::NZCVFlags )
// A64 Context getters/setters
A64OPC(SetCheckBit, T::Void, T::U1 )
@@ -230,8 +230,8 @@ OPCODE(FPAbs32, T::U32, T::U32
OPCODE(FPAbs64, T::U64, T::U64 )
OPCODE(FPAdd32, T::U32, T::U32, T::U32 )
OPCODE(FPAdd64, T::U64, T::U64, T::U64 )
OPCODE(FPCompare32, T::Void, T::U32, T::U32, T::U1 )
OPCODE(FPCompare64, T::Void, T::U64, T::U64, T::U1 )
OPCODE(FPCompare32, T::NZCVFlags, T::U32, T::U32, T::U1 )
OPCODE(FPCompare64, T::NZCVFlags, T::U64, T::U64, T::U1 )
OPCODE(FPDiv32, T::U32, T::U32, T::U32 )
OPCODE(FPDiv64, T::U64, T::U64, T::U64 )
OPCODE(FPMul32, T::U32, T::U32, T::U32 )