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IR: Implement IR instructions A64{Get,Set}S

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This commit is contained in:
MerryMage
2018-01-26 18:35:19 +00:00
parent 16fa2cd8f6
commit b513b2ef05
6 changed files with 28 additions and 2 deletions
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2
src/frontend/ir/microinstruction.cpp
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@@ -150,6 +150,7 @@ bool Inst::ReadsFromCoreRegister() const {
case Opcode::A32GetExtendedRegister64:
case Opcode::A64GetW:
case Opcode::A64GetX:
case Opcode::A64GetS:
case Opcode::A64GetD:
case Opcode::A64GetQ:
case Opcode::A64GetSP:
@@ -168,6 +169,7 @@ bool Inst::WritesToCoreRegister() const {
case Opcode::A32BXWritePC:
case Opcode::A64SetW:
case Opcode::A64SetX:
case Opcode::A64SetS:
case Opcode::A64SetD:
case Opcode::A64SetQ:
case Opcode::A64SetSP:

4
src/frontend/ir/opcodes.inc
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@@ -42,7 +42,7 @@ A64OPC(GetW, T::U32, T::A64Reg
A64OPC(GetX, T::U64, T::A64Reg )
//A64OPC(GetB, T::U128, T::A64Vec )
//A64OPC(GetH, T::U128, T::A64Vec )
//A64OPC(GetS, T::U128, T::A64Vec )
A64OPC(GetS, T::U128, T::A64Vec )
A64OPC(GetD, T::U128, T::A64Vec )
A64OPC(GetQ, T::U128, T::A64Vec )
A64OPC(GetSP, T::U64, )
@@ -50,7 +50,7 @@ A64OPC(SetW, T::Void, T::A64Reg, T::U32
A64OPC(SetX, T::Void, T::A64Reg, T::U64 )
//A64OPC(SetB, T::Void, T::A64Vec, T::U8 )
//A64OPC(SetH, T::Void, T::A64Vec, T::U16 )
//A64OPC(SetS, T::Void, T::A64Vec, T::U32 )
A64OPC(SetS, T::Void, T::A64Vec, T::U128 )
A64OPC(SetD, T::Void, T::A64Vec, T::U128 )
A64OPC(SetQ, T::Void, T::A64Vec, T::U128 )
A64OPC(SetSP, T::Void, T::U64 )