SwitchEmu/dynarmic
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/dynarmic.git synced 2026-03-07 17:36:27 +00:00
Code Issues Packages Projects Releases Wiki Activity

IR: Implement FPVectorSub

Browse Source
This commit is contained in:
MerryMage
2018-02-11 12:17:53 +00:00
parent 851fc83445
commit b9cd345ddc
5 changed files with 54 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/frontend/ir/ir_emitter.cpp
View File

@@ -1139,6 +1139,17 @@ U64 IREmitter::FPU32ToDouble(const U32& a, bool round_to_nearest, bool fpscr_con
return Inst<U64>(Opcode::FPU32ToDouble, a, Imm1(round_to_nearest));
}
U128 IREmitter::FPVectorSub(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 32:
return Inst<U128>(Opcode::FPVectorSub32, a, b);
case 64:
return Inst<U128>(Opcode::FPVectorSub64, a, b);
}
UNREACHABLE();
return {};
}
void IREmitter::Breakpoint() {
Inst(Opcode::Breakpoint);
}

2
src/frontend/ir/ir_emitter.h
View File

@@ -247,6 +247,8 @@ public:
U64 FPS32ToDouble(const U32& a, bool round_to_nearest, bool fpscr_controlled);
U64 FPU32ToDouble(const U32& a, bool round_to_nearest, bool fpscr_controlled);
U128 FPVectorSub(size_t esize, const U128& a, const U128& b);
void Breakpoint();
void SetTerm(const Terminal& terminal);

4
src/frontend/ir/opcodes.inc
View File

@@ -289,6 +289,10 @@ OPCODE(FPS32ToSingle, T::U32, T::U32, T::U1
OPCODE(FPU32ToDouble, T::U64, T::U32, T::U1 )
OPCODE(FPS32ToDouble, T::U64, T::U32, T::U1 )
// Floating-point vector instructions
OPCODE(FPVectorSub32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorSub64, T::U128, T::U128, T::U128 )
// A32 Memory access
A32OPC(ClearExclusive, T::Void, )
A32OPC(SetExclusive, T::Void, T::U32, T::U8 )