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A64: Implement SIMD instruction SSRA, vector variant

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MerryMage
2018-02-10 23:30:00 +00:00
parent f58aba9871
commit bd106c3ae7
2 changed files with 22 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@@ -779,7 +779,7 @@ INST(MOVI, "MOVI, MVNI, ORR, BIC (vector, immediate)", "0Qo01
// Data Processing - FP and SIMD - SIMD Shift by immediate
INST(SSHR_2, "SSHR", "0Q0011110IIIIiii000001nnnnnddddd")
//INST(SSRA_2, "SSRA", "0Q0011110IIIIiii000101nnnnnddddd")
INST(SSRA_2, "SSRA", "0Q0011110IIIIiii000101nnnnnddddd")
//INST(SRSHR_2, "SRSHR", "0Q0011110IIIIiii001001nnnnnddddd")
//INST(SRSRA_2, "SRSRA", "0Q0011110IIIIiii001101nnnnnddddd")
INST(SHL_2, "SHL", "0Q0011110IIIIiii010101nnnnnddddd")